Design Verification Lead

Apple Inc.; Austin (TX); On-site; USD 300,000 - 380,000; Full time

Job summary

Apple Inc. seeks a Senior Engineering Leader in Silicon Design Verification to guide one or more verification teams developing cutting‑edge silicon IPs. You will provide technical leadership, drive best practices, and ensure first‑pass success across performance, power, and area targets.

As a hands‑on leader you will mentor engineers, collaborate with architecture, design and software teams to define verification requirements, drive strategy, and implement test plans using SystemVerilog and UVM.

Qualifications

• BS and a minimum of 20 years relevant industry experience.
• Experience leading verification teams.
• Strong SystemVerilog and UVM expertise.
• Knowledge of UPF low-power verification and power intent validation.
• Background in high-speed interfaces (PCIe, USB, DDR) and multi-site leadership.

Responsibilities

• Lead, grow and mentor a team of verification engineers, providing technical guidance and performance assessment.
• Define verification requirements, drive strategy, planning, environment implementation and methodology.
• Develop and execute functional and power-aware verification plans, focusing on test coverage, formal verification, and assertion-based verification.
• Collaborate with architecture, design and software teams to ensure first-pass success of silicon designs.

Skills

SystemVerilog

UVM

Leadership

Verification strategy

Testbench development

Debugging

Cross-functional collaboration

Power/Performance awareness

Education

Bachelor's degree in Electrical Engineering or related

Tools

UPF methodology

Emulation

Formal verification

Job description

At Apple we push the boundaries of innovation to create extraordinary experiences for millions of users worldwide. We are seeking a Senior Engineering Leader – in the area of Silicon Design Verification to lead one or more high‑caliber verification teams in developing cutting‑edge silicon IPs. In this role, you will provide technical leadership, drive best practices, and ensure the first‑pass success of our silicon designs. You will play a crucial role in architecting verification methodologies, managing project execution, and fostering a culture of technical excellence within your teams.

Description

As a hands‑on leader you will work closely with cross‑functional teams to define and implement scalable, reusable, and efficient verification strategies. You will be expected to grow and guide a team of talented verification engineers, ensuring the highest quality silicon products that meet Apple’s performance, power, and area targets. Key responsibilities include but are not limited to lead, grow and mentor a team of verification engineers, providing technical guidance, career development, and performance management. Collaborate with architecture, design, and software teams to define verification requirements, drive verification strategy, planning, environment implementation and methodology. As well as define and execute functional and power‑aware verification plans, focusing on test coverage, formal verification, and assertion‑based verification using SystemVerilog and UVM methodologies. You also provide technical leadership by mentoring, reviewing team members' work, and fostering a culture of innovation and collaboration. And continuously refine verification strategies to improve efficiency, speed, and completeness.

Minimum Qualifications

• BS and a minimum of 20 years relevant industry experience.

Preferred Qualifications

• 12+ years of experience in ASIC/SoC verification, including at least 3 years in a senior leadership role managing teams of engineers.
• Experience with post‑silicon validation and debug.
• Familiarity with performance modeling, emulation, or prototyping.
• Hands‑on experience with low‑power design verification (UPF methodology, clock gating, power intent validation, etc.).
• Understanding of mixed‑signal interactions and analog modeling for verification.
• Background in high‑speed interfaces (e.g., PCIe, USB, DDR), power‑aware verification methodologies, formal verification, and constrained‑random testbenches.
• Proven track record of delivering high‑performance silicon with first‑pass success.
• Deep expertise in SystemVerilog, UVM, and modern verification methodologies.
• Strong debugging and problem‑solving skills for complex system‑on‑chip (SoC) designs.
• Experience leading multi‑site teams and cross‑functional collaboration with architecture, design, and software groups.
• Experience with coverage‑driven verification methodologies and regression‑driven verification strategies.
• Excellent communication and leadership skills, with a proven track record of developing high‑performing teams and mentoring engineers.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

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Apple accepts applications to this posting on an ongoing basis.