Senior Verification Engineer - Mixed-Signal ASICs & UVM

Cirrus Logic; Chandler (AZ); On-site; USD 100,000 - 130,000; Full time

Job summary

A prominent technology company in Chandler, Arizona seeks an experienced ASIC Verification Engineer. The role involves developing verification plans, conducting functional verification, and collaborating with cross-functional teams. Candidates must have a strong background in Verilog, VHDL, and SystemVerilog, as well as a degree in Electrical Engineering, with relevant experience based on the degree level. This position supports a dynamic environment with opportunities for professional growth.

Qualifications

• 10+ years of relevant experience for Bachelor's degree.
• 8+ years of relevant experience for Master's degree.
• 6+ years of relevant experience for PhD.
• Experience in silicon design and/or ASIC verification required.
• Hands-on experience with regression execution and coverage analysis.

Responsibilities

• Develop comprehensive verification plans for ASICs.
• Perform functional verification at block and chip level.
• Design and implement UVM-based testbenches.
• Conduct failure analysis and resolve timing-related issues.

Skills

Verilog

VHDL

SystemVerilog

UVM

ASIC verification

Digital design principles

Cross-disciplinary teamwork

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's degree with 8+ years experience

PhD with 6+ years experience

Job description

A prominent technology company in Chandler, Arizona seeks an experienced ASIC Verification Engineer. The role involves developing verification plans, conducting functional verification, and collaborating with cross-functional teams. Candidates must have a strong background in Verilog, VHDL, and SystemVerilog, as well as a degree in Electrical Engineering, with relevant experience based on the degree level. This position supports a dynamic environment with opportunities for professional growth.