Design Verification Engineer

WinMax Systems Corporation; Menlo Park (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

WinMax Systems Corporation located in Menlo Park, California is seeking an experienced candidate for FPGA Design Verification. You will develop verification tests, analyze results, and collaborate with engineers to resolve bugs.

The ideal applicant holds a BS or MS in a relevant field or has 7+ years of equivalent experience, and has expertise in System Verilog and UVM. Strong communication skills and collaboration across disciplines are essential.

Qualifications

• 7+ years of equivalent experience in ASIC or FPGA design verification.
• Experience solving technical problems in solo and team settings.
• Strong written and oral communication skills.

Responsibilities

• Develop FPGA Design Verification tests and test plans.
• Review Detailed Design specifications for logic to be tested.
• Execute tests, analyze results, and write bug reports.
• Work with IP vendors and Design engineers to resolve bugs.

Skills

FPGA Design Verification

System Verilog

UVM

Software design

TCL

Perl

Python

Bug tracking

Revision control

Build systems

Logic design using RTL techniques

Protocols and VIPs for PCIe, Ethernet, DRAM

Education

BS, MS in Computer Science or Electrical Engineering

Tools

Bugzilla

Git

Make

Job description

Responsibilities

Develop FPGA Design Verification tests, and test plans

Review Detailed Design specifications for logic to be tested

Execute tests, analyze results, review RTL, determine probably source of failures, write bug reports

Work with IP vendors and Design engineers to resolve bugs

Desired Skills and Experience

Expertise in ASIC or FPGA RTL design verification

Expertise in system Verilog, and UVM

Strong experience in software design, using classes

Developed and used scripting languages such as TCL, Perl, and Python

Experience with bug tracking (e.g. bugzilla), revision control (e.g. git), and build systems (e.g. make)

Working knowledge of logic design using RTL techniques

Familiar with Protocols and VIPs for PCIe, Ethernet, DRAM

Ability to interface with other disciplines, includng RTL/Logic, hardware design, and firmware engineers

Qualifications

BS, MS CS, EE or related discipline, or 7+ years of equivalent experience

History of solving technical problems, solo and in a team

Excellent written and oral communication skills

Additional Information

All your information will be kept confidential according to EEO guidelines.