Design verification Engineer

Scadea Solutions Inc; Allentown (Lehigh County); On-site; USD 90,000 - 130,000; Full time

Job summary

Scadea Solutions Inc. is seeking a Design Verification Engineer in Allentown, PA, to ensure that design functionalities meet requirements through detailed test plans. The ideal candidate will have over 5 years of experience in ASIC/SOC verification and be proficient in HVL-based verification.

Responsibilities include developing and executing verification plans, debugging complex simulations, and ensuring quality delivery. The role offers a chance to collaborate with cross-functional teams to achieve outstanding results.

Qualifications

• 5+ years of related industry experience in ASIC/SOC verification.
• Hands-on experience and expert level knowledge of HVL-based verification.

Responsibilities

• Create verification plans for various blocks.
• Develop the SoC/Subsystem Test case suite.
• Integrate SystemVerilog OVM test bench components.
• Develop system level scenarios for full chip.
• Debug complex chip simulations.
• Perform code and functional coverage analysis.
• Meet quality requirements for RTL release stages.

Skills

ASIC/SOC verification

HVL-based verification

Git version management

VCS

Questa CDC

Verdi

Job description

Job Description

Role: Design Verification Engineer

Location: Allentown, PA

Duration: Full-time

As a design verification engineer, you will be responsible for understanding expected design functionality, developing test plans and functional validation tests to verify that the system will meet design requirements. You will work closely with design engineers, architects and other team members to ensure high‑quality test plans and flawless test plan execution.

Responsibilities

• Verification plan creation for various blocks
• Develop the SoC/Subsystem Test case suite in various stages like RTL and GLS releases
• Integrate SystemVerilog OVM test bench components such as Scoreboard, Monitors, and Bus Function Models
• Develop system level scenarios for full chip
• Debug complex chip simulations and deliver bug‑free chip
• Perform code and functional coverage analysis for various subsystems
• Meet quality requirements before various RTL release stages

Qualifications

• 5+ years of related industry experience in ASIC/SOC verification
• Hands‑on experience and expert level knowledge of HVL‑based verification

Nice to Have

• Experience with Git version management tool
• Experience on VCS, Questa CDC, Verdi
• Ability to deliver high‑quality output against deadlines
• Ability to work effectively in cross‑site team environment