Design Verification Engineer

Yoh, A Day & Zimmermann Company; Santa Clara (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

A leading company in Silicon Valley is seeking a Design Verification Engineer to develop high-performance IO subsystems. The role involves collaborating with architecture and RTL teams, creating specifications, and optimizing designs. Ideal candidates will have extensive experience with IO protocols and a strong educational background in engineering.

Qualifications

• 5+ years of experience in IO subsystem design.
• Extensive experience with IO protocols such as PCIe, Ethernet, CXL.

Responsibilities

• Design and develop IO subsystems for high-performance SoC.
• Collaborate with design, test, and validation teams.

Skills

Problem Solving

Collaboration

Debugging

Education

BS/MS/PhD in EE/ECE/CE/CS

Tools

SystemVerilog

UVM

Job description

Direct message the job poster from Yoh, A Day & Zimmermann Company

Sr. Business Operations, Yoh Silicon Valley (Formerly ERG, Inc.)

Design Verification Engineer

Scope:
• Design and development of the IO subsystems for a high-performance SoC from scratch, working closely with the Architecture and RTL teams.
• Develop detailed block-level design specifications and plans for a high-performance IO Subsystem.
• Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers.
• Develop and optimize the IO subsystem design to ensure functionality and performance are in accordance with architectural specifications
• Evaluate and integrate open-source toolchains into the design flow.
• Collaborate with the design, test, and post-silicon validation teams to ensure high-quality delivery of the IO Subsystems

Required:
• BS/MS/PhD in EE/ECE/CE/CS with 5+ years of experience in IO subsystem design.
• Extensive experience with IO protocols such as PCIe, Ethernet, CXL, and die-to-die protocols (e.g., BoW, UCIe)
• Expertise in designing IO subsystems for CPU- and GPU-based architectures, with a deep understanding of protocols like PCIe, AXI, and CHI.
• Proven experience in tightly coupling hardware with CPUs, ensuring efficient memory access, optimized data paths, and seamless interaction between IO devices and processing cores
• Solid knowledge of PCIe architectural features: ordering rules, non-coherent flows, IO-device memory flows, peer-to-peer communication, bifurcation, and transaction types (posted vs. non-posted).
• Experience with Ethernet protocols, including MAC/PHY design, implementation of packet handling, flow control, and integration of TSN (Time-Sensitive Networking) features. Familiarity with Ethernet-based SoC architectures, low-latency optimizations, and debugging of Ethernet IP in hardware simulation environments using SystemVerilog and UVM for verification.
• Demonstrated problem-solving skills across complex design hierarchies, with the ability to debug and optimize in simulation environments.

Estimated Min Rate: $80.00
Estimated Max Rate: $90.00


Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit https://www.yoh.com/applicants-with-disabilitiesto contact us if you are an individual with a disability and require accommodation in the application process.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship, potentially resulting in the withdrawal of a conditional offer of employment.

Seniority level

• Seniority level

  Not Applicable

Employment type

• Employment type

  Contract

Job function

• Industries

  Computer Hardware Manufacturing and Software Development

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