Design Verification Engineer

Apple Inc.; Cupertino (CA); On-site; USD 151,000 - 215,000; Full time

Job summary

An established industry player is seeking a Design Verification Engineer to join their innovative team. In this role, you will interface with engineering teams to develop robust verification environments for cutting-edge SoC developments. You'll work closely with digital design teams, creating test benches and running simulations to ensure top-notch design quality. This position offers a competitive salary and comprehensive benefits, including stock options and educational reimbursements. If you're passionate about technology and eager to make a significant impact, this opportunity is perfect for you.

Benefits

Comprehensive medical and dental coverage

Retirement benefits

Discounted products and free services

Educational reimbursement

Employee stock purchase plan

Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field.
• Experience in Verilog and SystemVerilog for test development.

Responsibilities

• Develop verification environments for SoC developments.
• Run RTL and gate simulations and debug failures.

Skills

Verilog

SystemVerilog

C/C++

Perl

Python

TCL

Digital Electronics

RTL Design Concepts

System Verilog Assertions (SVA)

Education

Master’s degree in Electrical Engineering

Master’s degree in Computer Engineering

Tools

Simulators

Waveform Viewers

Job description

Cupertino, California, United States Hardware

Add to Favorites Design Verification Engineer

Removed from favorites

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Interface with the engineering digital design and analog to develop verification environments for SoC developments. Work closely with the digital design team to review and understand specifications, architecture and microarchitecture for block level and chip level verification. Develop test bench environment(s), directed and random/constrained tests to completely verify the design features. Come up with functional coverage metrics. Run RTL and gate simulations and debug/triage failures. Work with designers to come up with coverage waivers to achieve 100% code coverage. Develop reusable and scalable testbenches which can be easily integrated in higher level environments. Plan and develop the checkers to identify design bugs. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,091 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location.PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or related field.
• Education and/or experience must include the following skills:
• Using Verilog and SystemVerilog for constrained random test development
• Developing test plan and coverage plan
• Using C/C++ for reference model and checker development
• Perl, Python and TCL scripting for regression automation
• Knowledge of Digital Electronics and RTL design concepts
• Knowledge of simulators and waveform viewers for running tests and debugging digital designs
• Writing System Verilog Assertions (SVA) for simulations-based and formal verification

Preferred Qualifications

• N/A

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Add to Favorites Design Verification Engineer

Removed from favorites