Staff Digital Verification Engineer New San Jose, CA OR Pittsburgh, PA OR Remote

Efficient Computer Corporation, Inc.; San Jose (CA); Remote; USD 180,000 - 220,000; Full time

Job summary

Efficient Computer Corporation is seeking a Staff Digital Verification Engineer to influence the next computing revolution. This role involves verifying proprietary technology through UVM testbenches and collaborating with design teams. Join a high-trust, high-output team committed to shaping the future of computing.

Benefits

401K match

company-paid benefits

equity program

paid parental leave

flexibility

Qualifications

• Minimum 8+ years of experience in design verification.
• Experience writing and maintaining System Verilog test benches.

Responsibilities

• Write modular UVM testbenches and tests to verify design components.
• Collaborate with the digital design team to identify and fix bugs.

Skills

System Verilog

Python

UVM

Education

Bachelor’s degree in Engineering

Master’s degree or PhD

Job description

San Jose, CA OR Pittsburgh, PA OR Remote

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

Efficient is looking for a Staff Digital Verification (DV) Engineer who wants to influence the next computing revolution. We are seeking an engineer with industry experience to help us in our verification efforts for our first-generation product. The Staff DV Engineer will work on verifying Efficient’s proprietary Fabric technology by writing UVM testbenches, gathering and analyzing coverage reports, and contributing to the execution of the test plan. They will help shape our internal processes for building robust and verified designs, especially as the company scales up to higher-performance product lines.

This is a unique opportunity to get in at the ground level and have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Write modular UVM testbenches and tests to verify various design components.
• Use a constraint-random test methodology to effectively stimulate a device-under-test to increase coverage and find bugs.
• Write SystemVerilog assertions to check design invariants.
• Add cover points/groups to refine code coverage metrics.
• Collaborate with the digital design team to identify and fix bugs and coverage gaps.
• Support running gate-level simulations as part of design signoff.
• Support third-party vendor engineers when questions arise.
• Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.
• Assist in developing internal processes and frameworks to improve code quality, coverage, and correctness.

Required Qualifications & Experience

• Minimum 8+ years of experience in design verification.
• Experience writing and maintaining System Verilog test benches and test components
• Bachelor’s degree in Engineering or a related field is required; Master’s degree or PhD is a plus.
• Experience writing custom and reusable verification infrastructure components (e.g. drivers, monitors, agents, and models).
• Well-versed in coverage-driven, constrained random verification, including coverage analysis and coverage closure.
• Ability to analyze performance and correctness regressions to determine their root cause.
• Experience with script development for work automation, preferably experience with Python.
• Knowledge of UVM/OVM or equivalent portable verification methodologies, as well as IEEE-1801 (UPF) simulation flows is a plus
• Preferred:knowledge of computer architecture, processor design and implementation, hardware and software engineering, and software development toolchains.

We offer a competitive salary for this role, generally ranging from $180,000 to $220,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

At Efficient, we do not care about hierarchy—your impact is what matters. If you produce prodigious, high-quality work, you will be recognized and rewarded accordingly. We are a high-trust, high-output team where ownership and autonomy are paramount. If you are looking for a career-defining opportunity to shape the future of high-performance computing, let’s talk.

Efficient offers acompetitive compensation and benefits package, including401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.

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