Design Verification Engineer

YOH Services LLC; Santa Clara (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

An established industry player is seeking a Design Verification Engineer to create and optimize high-performance IO subsystems. This role involves collaborating with architecture and RTL teams, implementing reusable components, and ensuring quality through rigorous testing. The ideal candidate will have extensive experience with IO protocols like PCIe and Ethernet, as well as a strong background in SystemVerilog and UVM. Join this innovative firm to contribute to cutting-edge technology and advance your career in a dynamic environment.

Qualifications

• 5+ years of experience in IO subsystem design.
• Solid knowledge of PCIe features and protocols.

Responsibilities

• Design and develop IO subsystems for high-performance SoC.
• Collaborate with teams to ensure quality delivery of IO Subsystems.

Skills

IO subsystem design

PCIe protocols

Ethernet protocols

C++ programming

SystemVerilog

UVM

problem-solving

Education

BS/MS/PhD in EE/ECE/CE/CS

Tools

open-source toolchains

Job description

Design Verification Engineer

Category:

Engineering

Employment Type:

Contract

Reference:

BH-380904

Design Verification Engineer

Scope:

• Design and develop IO subsystems for high-performance SoC, collaborating with Architecture and RTL teams.
• Create detailed block-level design specifications and plans for IO Subsystem.
• Implement reusable block-level components in SV, UVM, and C++, including models, monitors, and checkers.
• Optimize IO subsystem design for functionality and performance according to architectural specs.
• Evaluate and integrate open-source toolchains into the design flow.
• Work with design, test, and validation teams to ensure quality delivery of IO Subsystems.

Required Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with 5+ years of IO subsystem design experience.
• Extensive experience with IO protocols such as PCIe, Ethernet, CXL, and die-to-die protocols (e.g., BoW, UCIe).
• Expertise in designing IO subsystems for CPU and GPU architectures, with understanding of protocols like PCIe, AXI, and CHI.
• Proven ability to integrate hardware with CPUs for efficient memory access and data paths.
• Solid knowledge of PCIe features: ordering, non-coherent flows, memory flows, peer-to-peer, bifurcation, transaction types.
• Experience with Ethernet protocols, MAC/PHY, packet handling, flow control, TSN, and hardware verification using SystemVerilog and UVM.
• Strong problem-solving skills in complex design hierarchies and simulation environments.

Estimated Rates: $80.00 - $90.00 per hour

Note: Pay ranges are estimations; actual pay depends on experience and qualifications. All qualified applicants are encouraged to apply.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. Consideration is given without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.

Visit https://www.yoh.com/applicants-with-disabilities for accommodation requests during the application process.

For California applicants, employment consideration complies with local laws regarding criminal records.