Design Engineering Architect

Cadence; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Cadence in Austin, Texas seeks an experienced Front End Design engineer to lead projects in the semiconductor industry. The role involves technical leadership, RTL development, and collaboration with cross-functional teams. Ideal candidates have over 10 years of experience in design and/or verification, including expertise in Verilog, project management, and IP integration. Competitive compensation and growth opportunities are offered.

Qualifications

• 10+ years of experience in Front End design and/or verification.
• Proven ability to lead and manage engineering projects.
• Rich experience in IP creation and SoC integration.

Responsibilities

• Guide and mentor a team of RTL design engineers.
• Define and develop microarchitectural features for IPs.
• Write, debug, and optimize RTL code in Verilog or VHDL.

Skills

Front End design

RTL design

Team Leadership

Verilog

Microarchitecture

Education

BS/MS in Engineering or Computer Sciences

Tools

Cadence front‑end toolset

Job description

Overview

The Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.

Responsibilities

• Technical Leadership: Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
• Design & Microarchitecture: Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
• RTL Development: Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
• Verification & Signoff: Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
• Collaboration: Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Qualifications

• 10+ years of Front End design and/or verification with a BS/MS in Engineering or Computer Sciences.
• Proven experience in leading and managing complex engineering projects.
• Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration.
• Expert in RTL design (Verilog), simulators and debuggers.
• Hands‑on experience in synthesis, SDC creation and support of PD and STA teams.
• Experience in driving results in a multi-disciplinary organization.

Desirable

• Self‑motivated person with good communication and design management skills.
• Experience with Cadence front‑end toolset.