Design Engineering Architect

Cadence Design Systems; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Job summary

Cadence Design Systems is seeking an experienced Front End Design leader to guide RTL teams and drive IP/SoC integration in a fast-paced semiconductor environment. You will mentor engineers, define microarchitectural features, and oversee RTL development, verification, and sign-off across cross-functional teams.

This leadership role blends technical depth with project management in a dynamic setting. Applicants should have 10+ years in Front End design or verification, with a track record of

Qualifications

• 10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
• Proven experience in leading and managing complex engineering projects
• Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration

Responsibilities

• Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
• Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
• Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
• Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
• Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Skills

RTL design Verilog

SystemVerilog

VHDL

Leadership

Mentoring

Education

BS/MS Engineering or Computer Sciences

Tools

Cadence front end toolset

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.

This is a leadership role where you will be responsible for:

Technical Leadership:

Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.

Design & Microarchitecture:

Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.

RTL Development:

Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.

Verification & Signoff:

Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.

Collaboration:

Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Qualifications:

• 10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
• Proven experience in leading and managing complex engineering projects
• Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
• Expert in RTL design (Verilog), simulators debuggers
• Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
• Experience in driving results in multi-disciplinary organization

Desirable:

A Self-motivated person with good communication and design management skills

Experience with Cadence front end toolset

We’re doing work that matters. Help us solve what others can’t.

We’re doing work that matters. Help us solve what others can’t.