Principal Design Engineer

Cadence; Cary (NC); On-site; USD 136,500 - 253,500; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision plans

Job summary

Cadence in Cary, North Carolina, is looking for an experienced engineer to lead implementations of SOCs or subsystem chips. The ideal candidate will have a strong background in RTL synthesis and optimizations, as well as experience with advanced technologies.

Responsibilities include leading team efforts, working on physical verification, and interfacing with design teams. A competitive salary range of $136,500 to $253,500 applies, along with comprehensive benefits.

Qualifications

• Minimum of 7 years of experience for BS, 5 years for MS, or 1 year for PhD.
• Experience with advanced technology nodes such as 5 nm and 3 nm.
• Familiarity with Linux servers.

Responsibilities

• Lead a team to implement SOCs or subsystem chips.
• Build clock trees and perform optimizations.
• Close timing and perform physical verification.

Skills

Leadership

RTL synthesis

Optimization techniques

Script development (Shell, Perl, TCL)

Knowledge of PCI Express, DDR, and SRAM

Education

BS in Electrical Engineering

MS with 5 years experience

PhD with 1 year experience

Tools

Cadence Innovus

Cadence Tempus

Cadence QRC

Cadence Voltus

Cadence Pegasus

Job description

Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health.

The Cadence Advantage

• The opportunity to work on cutting‑edge technology in an environment that encourages creativity, innovation, and impact.
• Employee‑friendly policies focused on physical and mental well‑being, career development, learning opportunities, and recognition of successes.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore based on individual needs and interests.
• A diverse team of passionate, dedicated, and talented individuals who go above and beyond for customers, communities, and each other—every day.

Job Responsibilities

• Lead a team to implement SOCs or subsystem chips.
• Work on RTL synthesis and floor planning.
• Build clock trees and perform optimizations.
• Close timing, IR drop, and physical verification.
• Review and document designs for tape‑out.
• Interface with Front End RTL design teams and Back End Verification teams.

Position Requirements / Qualifications

• BS degree in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum of 1 year of experience.
• Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus, and Pegasus.
• Experience with advanced technologies such as 5 nm, 3 ns, and 2 nm nodes.
• Experience using Linux servers and script development with Shell, Perl, or TCL.
• Detailed knowledge of industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.

Compensation and Benefits

Annual salary range for California is $136,500 to $253,500. Incentive compensation may include bonus, equity, and benefits. Sales positions generally offer a competitive on‑target earnings structure. Compensation may vary based on qualifications, skill level, and location.
Benefits include paid vacation and holidays, 401(k) plan with employer match, employee stock purchase plan, and a variety of medical, dental and vision plans.

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