Principal Design Engineer

Cadence; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Cadence, located in Austin, Texas, is seeking a Design Verification expert to lead subsystem and SOC verification efforts. Ideal candidates will have extensive experience with SV-UVM, ARM designs, and mentoring capabilities.

The role requires strong problem-solving abilities and a systematic approach to verification. Successful candidates will contribute significantly in a fast-paced environment, ensuring high-quality deliverables.

If you are passionate about making an impact in technology, join us at Cadence!

Qualifications

• Expertise in architecting, design and development of scalable verification environments.
• Experience with developing test cases and debugging to achieve coverage goals.
• Self-driven and committed individual who can thrive in fast-paced environments.

Responsibilities

• Independently verify complex modules and subsystems.
• Define verification methodology for SOC projects.
• Mentor junior engineers in independent verification.

Skills

Subsystem/SOC level verification projects

SV-UVM knowledge

ARM based designs

AMBA protocols (AXI, ACE, APB, AHB)

USB/PCIE/Ethernet/DDR/LPDDR protocols

Mentoring junior engineers

Problem solving skills

C based testcase development

Tools

Cadence tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experienced teammates. Should have worked on time-bounded projects leading to Si realization.

Independently handle verification of complex modules or own significant piece in subsystem / SOC based verification. Define methodology for subsystem/SOC verification. Mentor less experienced engineers to bring them up as independent verification engineer. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.

Required Experience

• Worked on Subsystem / SOC level verification projects
• Experience in ARM based designs.
• In-depth knowledge SV-UVM
• Expertise in architecting, design and development of scalable verification environments from scratch. Define verification architecture and verification strategy
• Expertise in verification test plan development, test cases coding; Execute and debug test cases to achieve functional and code coverage goals
• Experience in C based testcase development
• Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.
• Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols
• Strong problem solving skills. Exhibit discipline, thoroughness and methodical approach in solving problems
• Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
• Experience in mentoring junior engineers
• Self-driven and committed individual who can work in a fast paced project environment

Desirable Skills And Experience

• Prior experience with Cadence tools and flows is highly desirable
• Familiarity with ARM/CPU architectures is a plus
• Experience in developing c-based test cases for SOC verification
• Experience with assembly language programmingGood knowledge of some of the protocols like UART, I2C, SPI, JTAG
• Embedded C code development and debug
• Formal Verification experience
• Cadence verification tool experience

Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. A strong positive attitude and ability to work in a team is a must. Self-motivated and willing take up additional responsibilities to contribute to team’s success.

We’re doing work that matters. Help us solve what others can’t.