Group Director, Design Engineering - Front End

Cadence; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Job summary

Cadence seeks a Senior Front End Design Lead in Austin to guide RTL design teams and oversee front end verification. You will mentor engineers, drive schedules, and ensure quality from concept through sign-off.

Collaborate with DV, PD, architecture, and firmware to deliver complex IP and SoC integration. The role demands a track record of leading multi-disciplinary programs and hands-on expertise with synthesis, SDC, and Cadence front end tools.

Qualifications

• 10+ years of Front End design and/or verification experience
• Proven experience in leading and managing complex engineering projects
• Rich experience in IP creation and/or SoC and IP integration
• Hands on experience in Synthesis, SDC creation and support PD and STA teams
• Experience driving results in multi-disciplinary organizations

Responsibilities

• Technical Leadership: guide and mentor a team of RTL design engineers
• RTL Development: write, debug, and optimize RTL code in Verilog/SystemVerilog/VHDL
• Verification & Signoff: oversee pre-silicon verification activities and quality checks
• Cross-functional collaboration: work with DV, PD, Architecture, and firmware teams to ensure delivery

Skills

Front End design

RTL verification

Leadership

IP creation/SOC

Education

BS/MS Engineering or Computer Sciences

Tools

Cadence front end toolset

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.

This is a leadership role where you will be responsible for:

Technical Leadership

Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.

RTL Development

Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.

Verification & Signoff

Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.

Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.

Qualifications

• 10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
• Proven experience in leading and managing complex engineering projects
• Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
• Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
• Experience in driving results in multi-disciplinary organization

A Self-motivated person with good communication and design management skills

Experience with Cadence front end toolset