Front End Design Engineering Director

Cadence; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Job summary

Cadence seeks a Senior Front End Design Lead in Austin to guide RTL design teams and oversee front end verification. You will mentor engineers, drive schedules, and ensure quality from concept through sign-off.

Collaborate with DV, PD, architecture, and firmware to deliver complex IP and SoC integration. The role demands a track record of leading multi-disciplinary programs and hands-on expertise with synthesis, SDC, and Cadence front end tools.

Qualifications

• 10+ years of Front End design and/or verification experience
• Proven experience in leading and managing complex engineering projects
• Rich experience in IP creation and/or SoC and IP integration
• Hands on experience in Synthesis, SDC creation and support PD and STA teams
• Experience driving results in multi-disciplinary organizations

Responsibilities

• Technical Leadership: guide and mentor a team of RTL design engineers
• RTL Development: write, debug, and optimize RTL code in Verilog/SystemVerilog/VHDL
• Verification & Signoff: oversee pre-silicon verification activities and quality checks
• Cross-functional collaboration: work with DV, PD, Architecture, and firmware teams to ensure delivery

Skills

Front End design

RTL verification

Leadership

IP creation/SOC

Education

BS/MS Engineering or Computer Sciences

Tools

Cadence front end toolset

Job description

Cadence seeks a Senior Front End Design Lead in Austin to guide RTL design teams and oversee front end verification. You will mentor engineers, drive schedules, and ensure quality from concept through sign-off.

Collaborate with DV, PD, architecture, and firmware to deliver complex IP and SoC integration. The role demands a track record of leading multi-disciplinary programs and hands-on expertise with synthesis, SDC, and Cadence front end tools.