Senior Front-End Design Architect: RTL/SoC IP Leader

Cadence; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Cadence in Austin, Texas seeks an experienced Front End Design engineer to lead projects in the semiconductor industry. The role involves technical leadership, RTL development, and collaboration with cross-functional teams. Ideal candidates have over 10 years of experience in design and/or verification, including expertise in Verilog, project management, and IP integration. Competitive compensation and growth opportunities are offered.

Qualifications

• 10+ years of experience in Front End design and/or verification.
• Proven ability to lead and manage engineering projects.
• Rich experience in IP creation and SoC integration.

Responsibilities

• Guide and mentor a team of RTL design engineers.
• Define and develop microarchitectural features for IPs.
• Write, debug, and optimize RTL code in Verilog or VHDL.

Skills

Front End design

RTL design

Team Leadership

Verilog

Microarchitecture

Education

BS/MS in Engineering or Computer Sciences

Tools

Cadence front‑end toolset

Job description

Cadence in Austin, Texas seeks an experienced Front End Design engineer to lead projects in the semiconductor industry. The role involves technical leadership, RTL development, and collaboration with cross-functional teams. Ideal candidates have over 10 years of experience in design and/or verification, including expertise in Verilog, project management, and IP integration. Competitive compensation and growth opportunities are offered.