IC Design Engineer

Jobtailor; California (MO); On-site; USD 170,000 - 230,000; Full time

Job summary

Jobtailor is seeking a senior IC design engineer to lead synthesis and timing of complex designs, ensuring RTL quality and timely delivery. You will collaborate with RTL and PNR teams and interface with internal/external partners to drive physical implementation and power-intent requirements.

The role emphasizes hands-on frontend tool expertise (PrimeTime, DC, VCLP, Formality, LEC) and scripting (TCL) to optimize timing closure, constraints development, and overall flow correctness across the

Qualifications

• Bachelor’s in Engineering and 12+ years of related experience or Master’s degree in Engineering and 10+ years of related experience
• Timing closure and timing knowledge
• Good in TCL scripting

Responsibilities

• Leading a synthesis and timing of complex designs
• Provide guidance, interface with RTL team for quality RTL delivery
• Full chip and block constraints development and constraints generation
• Full chip and block synthesis, STA and timing closure
• Interfacing with internal and external teams including Design, IP, Library Methodology & Flow development
• Working independently with the PNR & RTL design team on physical implementation and power‑intent requirements

Skills

Timing closure

TCL scripting

Leadership

Education

Bachelor’s in Engineering

Master’s in Engineering

Tools

Primerime

DC

VCLP

Formality

LEC

Job description

Responsibilities

• Leading a synthesis and timing of complex designs
• Provide guidance, interface with RTL team for quality RTL delivery
• Full chip and block constraints development and constraints generation
• Full chip and block synthesis, STA and timing closure
• Interfacing with internal and external teams including Design, IP, Library Methodology & Flow development
• Working independently with the PNR & RTL design team on physical implementation and power‑intent requirements

Requirements

• Bachelor’s in Engineering and 12+ years of related experience or Master’s degree in Engineering and 10+ years of related experience
• Extensive experience in frontend tools such as Primerime, DC, VCLP, Formality, LEC
• Timing closure and timing knowledge
• Good in TCL scripting

Core Competencies

Demonstrates expertise in leading synthesis and timing of complex designs, ensuring quality RTL delivery and timing closure through effective collaboration with RTL and PNR teams. Proficient in frontend tools and scripting to support physical implementation and power‑intent requirements.