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Apple Inc. is seeking a DDR Design Engineer to join the DDR PHY design team in California. You will participate in all phases from concept study to silicon bring‑up, delivering high‑quality RTL and supporting verification and timing closure.
The role emphasizes RTL design using Verilog/SystemVerilog, assertion writing, and experience with DDR PHY design in a mixed‑signal environment. Apple offers competitive compensation and a broad benefits package.
Apple Inc. is seeking a DDR Design Engineer to join the DDR PHY design team in California. You will participate in all phases from concept study to silicon bring‑up, delivering high‑quality RTL and supporting verification and timing closure.
The role emphasizes RTL design using Verilog/SystemVerilog, assertion writing, and experience with DDR PHY design in a mixed‑signal environment. Apple offers competitive compensation and a broad benefits package.