SoC Interconnect & RTL Design Engineer

Apple, Inc.; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple seeks a design engineer to drive RTL development, fabric integration and memory subsystem optimization for SoC blocks. You will own RTL generation, templating and scripting while coordinating with front-end, power and verification teams to ensure timing and quality.

The role requires collaboration with multi-disciplinary groups to deliver high-quality designs on schedule, with a strong emphasis on coherent/non-coherent interconnects and memory hierarchy.

Qualifications

• BS degree required with 0 years of experience.

Responsibilities

• Design & Integration of coherent and non-coherent fabrics into a subsystem or SoC.
• Own RTL development design, templating, scripting and RTL generation.
• Collaborate with group to deliver results and hit schedules.

Skills

Cache Coherency

Memory Hierarchy

Large Designs

Synthesis & Verification

Interpersonal Skills

Self-starter

Front-end Tools

Education

BS Degree

Job description

Apple seeks a design engineer to drive RTL development, fabric integration and memory subsystem optimization for SoC blocks. You will own RTL generation, templating and scripting while coordinating with front-end, power and verification teams to ensure timing and quality.

The role requires collaboration with multi-disciplinary groups to deliver high-quality designs on schedule, with a strong emphasis on coherent/non-coherent interconnects and memory hierarchy.