DDR PHY Design Engineer — RTL, Timing & Silicon Bring-Up

Apple Inc.; Austin (TX); On-site; USD 130,000 - 190,000; Full time

Job summary

Apple Inc. in Austin, TX is seeking a results-oriented DDR Design Engineer to join the DDR PHY design team.

You will contribute across the full cycle—from concept study and architecture definition to synthesis, verification, silicon bring-up and characterization. You will provide RTL in Verilog/SystemVerilog, including assertions, and write detailed design specs and test plans in collaboration with architecture, circuit and verification engineers.

Qualifications

• Bachelor's degree in Electrical Engineering required.
• Experience with RTL design in Verilog or SystemVerilog preferred.
• Knowledge of design for test (DFT) and scan concepts is a plus.

Responsibilities

• Provide high-quality RTL descriptions, including assertions, for DDR PHY designs.
• Write detailed design specifications and test plans in collaboration with architecture, circuit and verification engineers.
• Drive functional and code coverage, timing closure, and silicon bring-up efforts.

Skills

Verilog

SystemVerilog

RTL design

Assertions

DFT

Education

Bachelor's degree in Electrical Engineering

Job description

Apple Inc. in Austin, TX is seeking a results-oriented DDR Design Engineer to join the DDR PHY design team.

You will contribute across the full cycle—from concept study and architecture definition to synthesis, verification, silicon bring-up and characterization. You will provide RTL in Verilog/SystemVerilog, including assertions, and write detailed design specs and test plans in collaboration with architecture, circuit and verification engineers.