Senior Physical Design Engineer: High-Performance PHY

Apple, Inc.; United States; On-site; USD 175,000 - 309,000; Full time

Job summary

Apple Inc. is seeking a forward-thinking Physical Design Engineer to drive high-performance PHY design from RTL to GDSII. You will collaborate across architecture, CAD, timing, and logic teams to deliver outstanding PHY designs for Apple’s products.

The role emphasizes block/chip level constraints, floor-planning, and flow development, with a focus on power and timing. A strong Verilog background and Scripting skills are essential.

Qualifications

• BS in Electrical Engineering with 10+ years of relevant industry experience.
• Experience in high PHY and/or SOC designs.
• Knowledge of physical design practices including synthesis, floor-planning, and Place & Route.
• Experience developing and implementing Power-grid and Clock specifications.
• Strong HDL knowledge (Verilog) and timing fixes with design teams.

Responsibilities

• Generate block/chip level static timing constraints.
• Build full chip floor-plan including pin placement, partitions, and power grid.
• Perform block level place and route and meet timing, area and power constraints.
• Generate and implement ECOs to fix timing, noise and EM IR violations.
• Run physical design verification flow and guide LVS/DRC fixes.
• Contribute to CAD and physical design methodologies for correct-by-construction designs.
• Assist in flow development for chip integration.

Skills

PHY design

SoC design

Timing constraints

Floor-planning

Place & Route

Power integrity

Verilog

Perl/Tcl scripting

Education

Bachelor's degree in Electrical Engineering

Tools

Physical Design tools

STA & DRC/LVS tooling

Job description

Apple Inc. is seeking a forward-thinking Physical Design Engineer to drive high-performance PHY design from RTL to GDSII. You will collaborate across architecture, CAD, timing, and logic teams to deliver outstanding PHY designs for Apple’s products.

The role emphasizes block/chip level constraints, floor-planning, and flow development, with a focus on power and timing. A strong Verilog background and Scripting skills are essential.