DDR PHY Design Engineer: High-Performance RTL & Power

Apple Inc.; Waltham (MA); On-site; USD 116,400 - 203,000; Full time

Benefits offered by this job

Apple stock program

Relocation assistance

Tuition reimbursement

Medical and dental coverage

Retirement benefits

Discounted products

Job summary

Apple Inc. in Waltham, MA is seeking a DDR Design Engineer to join the DDR PHY design team. You will contribute to high-performance, low-power digital designs from concept through silicon bring-up.

You will write detailed specifications and RTL with assertions, perform design verification, and help achieve timing closure while optimizing gate count, performance and power. A BS in Electrical Engineering and Verilog/SystemVerilog experience are preferred.

Qualifications

• RTL design experience with Verilog or SystemVerilog.
• Experience writing assertions and formal checks.
• Knowledge of state machines, data paths, and clock domain crossing.
• Familiarity with timing constraints and logic synthesis.

Responsibilities

• Perform concept studies and guide performance, gate count and power decisions.
• Write detailed design specifications and test plans with architecture teams.
• Provide high-quality RTL with assertions; use formal tools for RTL quality.
• Support design verification and silicon bring-up; drive timing closure.

Skills

RTL design

Verilog/SystemVerilog

Assertions

Clock domain crossing

Timing constraints

DFT RTL

DDR PHY design

Education

Bachelors in Electrical Engineering

Job description

Apple Inc. in Waltham, MA is seeking a DDR Design Engineer to join the DDR PHY design team. You will contribute to high-performance, low-power digital designs from concept through silicon bring-up.

You will write detailed specifications and RTL with assertions, perform design verification, and help achieve timing closure while optimizing gate count, performance and power. A BS in Electrical Engineering and Verilog/SystemVerilog experience are preferred.