CPU Timing Closure Engineer for Oryon Cores

Qualcomm; Santa Clara (CA); On-site; USD 142,200 - 213,400; Full time

Benefits offered by this job

Discretionary bonus

RSU grants

Competitive benefits

Job summary

Qualcomm Technologies, Inc. seeks a CPU Physical Design Timing Engineer to define, develop and drive timing closure for Oryon CPU Cores. You will work with RTL and timing teams to meet aggressive power, area and performance goals on advanced nodes.

You will build automation scripts (TCL/Perl/Python), run PrimeTime/Tempus, and contribute to timing methodology across multiple CPU projects, driving PPA improvements. Strong STA experience and RTL-to-GDS flow knowledge are essential.

Qualifications

• Minimum qualifications as described: degrees with 2+ years of relevant experience (Bachelor), 1+ year with a Master, or any PhD in the field.
• Expertise in STA timing analysis basics and timing constraint definitions.
• Hands-on experience with STA tools like PrimeTime and Tempus.
• Experience driving timing convergence at chip-level and hard-macro level.
• Knowledge of ASIC back-end flows, cross-talk, and layout parasitics.
• Scripting with TCL/Perl/Python for automation in STA/PD environments.

Responsibilities

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage designs of Oryon CPU Cores.
• Timing analysis, validation and debugging across multiple PVT conditions using PT/Tempus.
• Run PrimeTime and Tempus for STA flow optimization and Spice-to-STA correlation.
• Identify root causes of timing miscorrelation across design levels and propose solutions.
• Evaluate timing methodologies/tools across designs and nodes.
• Develop automation scripts within STA/PD tools for methodology development.
• Collaborate cross-functionally with timing technology teams and CPU implementation.
• Communicate findings clearly and maintain documentation.

Skills

STA timing analysis

Timing convergence

Signal integrity

Cross-talk knowledge

Device physics knowledge

Scripting languages

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

PrimeTime

Tempus

ICC2

Innovus

TCL

Perl

Python

Job description

Qualcomm Technologies, Inc. seeks a CPU Physical Design Timing Engineer to define, develop and drive timing closure for Oryon CPU Cores. You will work with RTL and timing teams to meet aggressive power, area and performance goals on advanced nodes.

You will build automation scripts (TCL/Perl/Python), run PrimeTime/Tempus, and contribute to timing methodology across multiple CPU projects, driving PPA improvements. Strong STA experience and RTL-to-GDS flow knowledge are essential.