CPU Server Physical Design Timing Engineer

Qualcomm; Santa Clara (CA); On-site; USD 142,200 - 213,400; Full time

Benefits offered by this job

Discretionary bonus

RSU grants

Competitive benefits

Job summary

Qualcomm Technologies, Inc. seeks a CPU Physical Design Timing Engineer to define, develop and drive timing closure for Oryon CPU Cores. You will work with RTL and timing teams to meet aggressive power, area and performance goals on advanced nodes.

You will build automation scripts (TCL/Perl/Python), run PrimeTime/Tempus, and contribute to timing methodology across multiple CPU projects, driving PPA improvements. Strong STA experience and RTL-to-GDS flow knowledge are essential.

Qualifications

• Minimum qualifications as described: degrees with 2+ years of relevant experience (Bachelor), 1+ year with a Master, or any PhD in the field.
• Expertise in STA timing analysis basics and timing constraint definitions.
• Hands-on experience with STA tools like PrimeTime and Tempus.
• Experience driving timing convergence at chip-level and hard-macro level.
• Knowledge of ASIC back-end flows, cross-talk, and layout parasitics.
• Scripting with TCL/Perl/Python for automation in STA/PD environments.

Responsibilities

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage designs of Oryon CPU Cores.
• Timing analysis, validation and debugging across multiple PVT conditions using PT/Tempus.
• Run PrimeTime and Tempus for STA flow optimization and Spice-to-STA correlation.
• Identify root causes of timing miscorrelation across design levels and propose solutions.
• Evaluate timing methodologies/tools across designs and nodes.
• Develop automation scripts within STA/PD tools for methodology development.
• Collaborate cross-functionally with timing technology teams and CPU implementation.
• Communicate findings clearly and maintain documentation.

Skills

STA timing analysis

Timing convergence

Signal integrity

Cross-talk knowledge

Device physics knowledge

Scripting languages

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

PrimeTime

Tempus

ICC2

Innovus

TCL

Perl

Python

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > CPU Engineering

General Summary:

NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.

About The Role:

In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU. You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3.

Key Responsibilities:

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.


• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.


• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.


• Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.


• Evaluate multiple timing methodologies/tools on different designs and technology nodes.


• Work on automation scripts within STA/PD tools for methodology development.


• Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment


• Strong experience in design automation using TCL/Perl/Python.


• Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.


• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.


• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Preferred Qualification/Skills:

• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling


• Hands-on experience with STA tools - Prime-time, Tempus


• Have experience in driving timing convergence at Chip-level and Hard-Macro level


• In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling


• Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)


• Expert in scripting languages – TCL, Perl, Python


• Basic knowledge of device physics

Pay range and Other Compensation & Benefits:

• $142,200.00 - $213,400.00


• We also offer a competitive annual discretionary bonus program


• and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).


• In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.