ASIC Timing Implementation Engineer - Timing Closure

Meta; Sunnyvale (CA); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer focusing on timing to drive static timing analysis and timing closure for advanced process nodes in data center chips. You will collaborate across front-end and back-end to meet performance, power, and area targets at 7nm and beyond.

Responsibilities include creating timing constraints, conducting sign-off timing with PrimeTime, and guiding RTL and physical implementation optimizations.

Qualifications

• Experience with static timing analysis and timing closure.
• Experience developing and validating timing constraints for complex SoC designs.

Responsibilities

• Develop and maintain timing constraints (SDC) for complex SoC designs.
• Perform static timing analysis to identify setup/hold violations across blocks.
• Drive timing closure through collaboration with physical design engineers for placement, routing and_clock tree synthesis.
• Analyze timing paths across multiple clock domains and optimize RTL or physical implementations.
• Generate and validate timing reports for sign-off across corners including on-chip variation.

Skills

Python scripting

Tcl scripting

Perl scripting

Education

Bachelor's degree in Computer Science or Electrical Engineering

Tools

PrimeTime

Job description

Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer focusing on timing to drive static timing analysis and timing closure for advanced process nodes in data center chips. You will collaborate across front-end and back-end to meet performance, power, and area targets at 7nm and beyond.

Responsibilities include creating timing constraints, conducting sign-off timing with PrimeTime, and guiding RTL and physical implementation optimizations.