CPU Physical Design Timing Engineer (Austin, TX)

Qualcomm; Austin (TX); On-site; USD 122,500 - 183,700; Full time

Benefits offered by this job

Competitive discretionary bonus program

Annual RSU grant opportunities

Comprehensive benefits

Job summary

Qualcomm is seeking a CPU Physical Design Timing Engineer to define and drive CPU timing closure for Oryon CPU Cores in Austin, Texas. The role involves working with talented engineers to develop timing constraints and implement methodologies across multiple CPU projects.

The ideal candidate will have a Bachelor’s degree in Electrical Engineering or related fields and a strong skill set in STA tools. Competitive pay range is $122,500 - $183,700 with additional benefits.

Qualifications

• 2+ years of related work experience for Bachelor's degree.
• 1+ year for Master's degree or PhD in same field.
• Willingness to work in a cross-collaborative environment.

Responsibilities

• Drive CPU timing closure for Oryon CPU Cores.
• Conduct STA setup, convergence, reviews and signoff.
• Perform timing analysis, validation and debug across multiple conditions.
• Run Primetime and/or Tempus for STA flow optimization.
• Propose solutions for timing miscorrelation.

Skills

Excellent automation skills using TCL/Perl/Python

Experience in framework/tool/utility development preferred

Strong expertise in STA timing analysis basics

Hands-on experience with STA tools – Prime-time, Tempus

In-depth knowledge of crosstalk noise

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field

Master's degree in same field

PhD in same field

Tools

STA tools – Prime-time, Tempus

ICC, Innovus

Job description

General Summary

NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.

About The Role

In this role you will define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you work with microarchitecture and RTL design team to develop timing constraints, drive implementation to meet aggressive power, area and performance goals using industry standard tools/flows. You will code scripts used with STA native tools and enable CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will collaborate with Qualcomm central timing technology and methodology team and interact with CPU implementation team to drive PPA goals.

Mandatory Skill Set Required for this position

• Excellent automation skills using TCL/Perl/Python
• Ability to develop/work on automation scripts with the given spec to develop CPU STA signoff flow/methodology
• Experience in framework/tool/utility development preferred

Responsibilities

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores
• Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus
• Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation
• Find root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions
• Evaluate multiple timing methodologies/tools on different designs and technology nodes
• Good technical writing and communication skills, willing to work in cross‑collaborative environment
• Familiar with digital flow design implementation RTL to GDS: ICC, Innovus, PT/Tempus

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field and 2+ years of related work experience
• Master's degree in same field and 1+ year of related experience OR PhD in same field

Preferred Qualification/Skills

• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, latch transparency handling, 0‑cycle and multi‑cycle path handling
• Hands‑on experience with STA tools – Prime‑time, Tempus
• Experience in driving timing convergence at chip‑level and hard‑macro level
• In‑depth knowledge of crosstalk noise, signal integrity, layout parasitic extraction, feed‑through handling
• Knowledge of ASIC back‑end design flows and methods and tools – ICC2, Innovus
• Basic knowledge of device physics

Equal Opportunity Employment

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may email disability‑[e-mail] for assistance. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

EEO Employer Statement

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.

Pay Range and Other Compensation & Benefits

$122,500.00 - $183,700.00. This range reflects the broad minimum to maximum pay scale for this position. In addition to base salary, the role includes a competitive discretionary bonus program and annual RSU grant opportunities. Benefits are available to support success at work, home, and play.