Senior CPU Timing & Automation Engineer (Oryon Core)

Qualcomm; Santa Clara (CA); On-site; USD 199,000 - 298,000; Full time

Job summary

Qualcomm Technologies, Inc. in Santa Clara seeks a CPU Physical Design Timing Engineer to define, develop, and drive CPU timing closure for Oryon CPU Cores.

You will work with RTL and microarchitecture teams to implement timing constraints and meet aggressive power/area/performance goals using industry standard tools. You will script STA workflows, collaborate with central timing tech teams, and contribute to PPA targets across multiple CPU projects on advanced nodes N2/N3.

Qualifications

• Bachelor's degree with 6+ years of relevant hardware/software experience.
• Master's degree with 5+ years of relevant hardware/software experience.
• PhD with 4+ years of relevant hardware/software experience.
• Strong STA timing analysis fundamentals and tool experience (STA).

Responsibilities

• STA setup, convergence, reviews and signoff for multi-mode, multi-voltage designs.
• Timing analysis, validation and debugging across multiple PVT conditions.
• Run PrimeTime and Tempus for STA flow optimization and correlation.
• Identify root causes of timing mismatches and propose solutions.
• Evaluate timing methodologies/tools across designs and nodes.
• Collaborate cross-functionally to drive PPA goals.

Skills

TCL/Perl/Python

Automation scripting

Framework/tool development

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

ICC2

Innovus

Primetime

Tempus

Job description

Qualcomm Technologies, Inc. in Santa Clara seeks a CPU Physical Design Timing Engineer to define, develop, and drive CPU timing closure for Oryon CPU Cores.

You will work with RTL and microarchitecture teams to implement timing constraints and meet aggressive power/area/performance goals using industry standard tools. You will script STA workflows, collaborate with central timing tech teams, and contribute to PPA targets across multiple CPU projects on advanced nodes N2/N3.