CPU Verification Architect: SV/UVM, ISA & Testbenches

RosaicLabs Inc; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, Dental, Vision

401(k)

Life & AD&D

Job summary

RosaicLabs Inc. in Austin, TX seeks a CPU verification engineer to drive verification strategy, build SystemVerilog/UVM testbenches, and rigorously verify CPU blocks against ISA references. You will develop directed and pseudo-random tests, close functional/code coverage, and debug RTL/testbench issues with cross-functional teams.

Qualifications include a BS/MS in EE/CS, strong SystemVerilog/C/C++, and scripting (Python). Experience with coverage, regression, and emulation is preferred.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering, Computer Engineering, Computer Science or related.
• Working knowledge of a modern ISA including familiarity with ISA simulators or reference models.
• Hands-on SystemVerilog experience, including testbench development (UVM preferred); assertions and functional coverage.

Responsibilities

• Drive CPU verification strategy, develop test plans for functional blocks based on specifications targeting micro-architectural & ISA features.
• Architect, build and maintain SystemVerilog/C++ based testbench components, including stimulus generators, checkers, scoreboards, monitors, and reference models.
• Develop directed and pseudo-random tests from Random Instruction Generators to verify CPU functionality and stress corner cases.
• Define, implement, and close functional and code coverage goals, analyzing holes and driving them to closure.
• Debug & root-cause failures across RTL, testbench, and reference models, and work with RTL designers to root-cause and resolve bugs.
• Partner cross-functionally with RTL design, performance modeling, CAD/methodology, and software teams to align on verification strategy, improve tools and flows, and drive shared quality, schedule, and tape-out goals.
• Apply formal verification, assertions (SVA), and emulation where appropriate to improve verification quality and efficiency.
• Run and maintain regressions across various platforms including Simulation, Emulation, FPGA’s and track bug trends and verification progress metrics.
• Participate in microarchitecture, RTL, and verification reviews and write technical documentation.

Skills

SystemVerilog

C/C++

ISA familiarity

Scripting (Python)

Testbench development

Education

BS/MS in Electrical/Computer Engineering or related

Tools

SystemVerilog

UVM

C/C++

Job description

RosaicLabs Inc. in Austin, TX seeks a CPU verification engineer to drive verification strategy, build SystemVerilog/UVM testbenches, and rigorously verify CPU blocks against ISA references. You will develop directed and pseudo-random tests, close functional/code coverage, and debug RTL/testbench issues with cross-functional teams.

Qualifications include a BS/MS in EE/CS, strong SystemVerilog/C/C++, and scripting (Python). Experience with coverage, regression, and emulation is preferred.