CPU RTL Microarchitecture/Design Engineer - Full Time

RosaicLabs Inc; Austin (TX); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical (incl. HSA)

Dental

Vision

Life & AD&D

401(k)

Job summary

RosaicLabs Inc. is seeking an experienced hardware engineer to design and implement CPU functional blocks and optimize RTL using SystemVerilog/Verilog.

You will analyze tradeoffs in performance, timing, and power while collaborating with verification and physical design teams to meet area and timing goals. The role requires a strong understanding of computer architecture, DSP/CPU fundamentals, and hands-on RTL experience, along with scripting skills (Python/Tcl) to support automation and test

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Strong foundation in computer architecture and digital design with knowledge of key areas.
• Hands-on Verilog/SystemVerilog experience including RTL simulation and testbench debugging.
• Familiarity with the ASIC design flow: RTL design, verification, synthesis, timing analysis.

Responsibilities

• Design and implement CPU functional blocks based on microarchitecture specifications.
• Develop, debug, and optimize RTL using SystemVerilog/Verilog.
• Analyze performance, timing, area, and power tradeoffs and propose improvements.
• Work with verification engineers to develop test plans and achieve functional coverage.
• Partner with physical design engineers on area, timing, and power goals.
• Participate in microarchitecture and RTL design reviews and write technical documentation.

Skills

CPU architecture

Verilog/SystemVerilog

Digital design

Automation scripting

Education

Electrical Engineering

Computer Engineering

Tools

Python

Tcl

C/C++

Job description

• Design and implement CPU functional blocks based on microarchitecture specifications
• Develop, debug, and optimize RTL using SystemVerilog/Verilog
• Analyze performance, timing, area, and power tradeoffs and propose improvements
• Work with verification engineers to develop test plans and achieve functional coverage
• Partner with physical design engineers on area, timing, and power goals
• Participate in microarchitecture and RTL design reviews and write technical documentation

What you'll do

• Design and implement CPU functional blocks based on microarchitecture specifications
• Develop, debug, and optimize RTL using SystemVerilog/Verilog
• Analyze performance, timing, area, and power tradeoffs and propose improvements
• Work with verification engineers to develop test plans and achieve functional coverage
• Partner with physical design engineers on area, timing, and power goals
• Participate in microarchitecture and RTL design reviews and write technical documentation

What we're looking for

• Bachelor's or Master's degree (or near-term graduation) in one of:
  • Electrical Engineering
  • Computer Engineering
  • Computer Science
  • A related field
• Strong foundation in computer architecture and digital design, with solid understanding of at least two of the following:
  • Out-of-order execution
  • CPU front-end / control logic
  • Load/store and memory systems
  • Cache hierarchy and coherency
  • Virtual memory
  • Floating-point / computer arithmetic
  • SIMD / vector processing
• Working knowledge of a modern ISA
• Hands-on Verilog/SystemVerilog experience, including:
  • RTL simulation
  • Testbench-based debugging
• Familiarity with the ASIC design flow:
  • RTL design
  • Verification
  • Synthesis
  • Timing analysis
• Scripting experience for automation, test generation, or data analysis, such as: Python, Perl, Tcl or C/C++

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

Benefits: Medical (including HSA plans), Dental, Vision, Employee Life & AD&D, 401(k)