RTL Power Management Engineer for Next-Gen CPUs

Advanced Micro Devices; Santa Clara (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

AMD in Santa Clara, CA is seeking an experienced RTL design engineer to architect core clocking, reset, and power management IP for next‑gen processors. You will implement RTL in Verilog/SystemVerilog and develop firmware in C/C++ for IP initialization and control.

The role requires a MS in EE/CS and 5+ years in RTL design, with strong debugging skills, cross‑team collaboration, and a passion for power‑aware design and DVFS. Hybrid/onsite options eligible.

Qualifications

• MS in EE/ECE/Computer Engineering, or Computer Science with 5+ years of RTL design experience.
• Proficiency in Verilog/SystemVerilog for RTL design and verification.
• Strong C/C++ development experience, including embedded firmware for power management.
• Solid understanding of digital design fundamentals: synchronous/asynchronous design, CDC, multi-voltage, and power-aware design.
• Knowledge of low-power methodologies (clock gating, power gating, DVFS).
• Proven debugging skills across RTL and firmware; effective communication and teamwork.

Responsibilities

• Design and develop microarchitecture for core clocking, reset, and power management IP in next-generation processors.
• Collaborate with architecture, design verification, physical design, and firmware teams to integrate IP into the overall processor using cutting-edge process technologies.
• Define specifications and documentation for IP microarchitecture and interfaces.
• Implement RTL in Verilog/SystemVerilog optimized for timing, area, power, and performance.
• Develop C/C++ firmware for IP initialization, configuration, and control; partner with firmware engineers to ensure seamless integration.
• Perform RTL linting, clock domain crossing (CDC) analysis, and related checks for design correctness.
• Work with verification to build comprehensive test plans and ensure functional correctness.
• Debug complex RTL and firmware issues; drive resolution across cross-functional teams.
• Participate in design reviews and contribute to continuous improvement of quality and efficiency.

Skills

RTL design

Verilog/SystemVerilog

C/C++ development

Embedded firmware

DVFS/power management

Clock gating

Debugging

Team collaboration

Education

MS in EE/ECE/CE/CS

Job description

AMD in Santa Clara, CA is seeking an experienced RTL design engineer to architect core clocking, reset, and power management IP for next‑gen processors. You will implement RTL in Verilog/SystemVerilog and develop firmware in C/C++ for IP initialization and control.

The role requires a MS in EE/CS and 5+ years in RTL design, with strong debugging skills, cross‑team collaboration, and a passion for power‑aware design and DVFS. Hybrid/onsite options eligible.