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Intel Corporation's HIPD team seeks a senior Logic Design Engineer to join the UCIE PHY IP for data-center/server designs. You will develop RTL, participate in architecture and microarchitecture feature definition, and optimize for power, performance and area.
Responsibilities include RTL coding, timing/power convergence checks, review of verification plans, and ensuring RTL tests pass. This role supports a hybrid work model across US sites including Santa Clara, Hillsboro, Phoenix, and more.
Intel Corporation's HIPD team seeks a senior Logic Design Engineer to join the UCIE PHY IP for data-center/server designs. You will develop RTL, participate in architecture and microarchitecture feature definition, and optimize for power, performance and area.
Responsibilities include RTL coding, timing/power convergence checks, review of verification plans, and ensuring RTL tests pass. This role supports a hybrid work model across US sites including Santa Clara, Hillsboro, Phoenix, and more.