CPU Core Verification Engineer Intern

RosaicLabs Inc; Santa Clara (CA); On-site; USD 28,000 - 41,000; Full time

Job summary

RosaicLabs Inc. in Santa Clara, CA is seeking an undergraduate or graduate student for an internship/co-op in hardware verification.

You will develop verification plans for CPU cores and cache hierarchies under a mentor, write and debug SystemVerilog/UVM testbenches, and build scoreboards and references to close coverage. You will gain hands-on exposure to chip design and verification, work with RTL designers to triage failures, and participate in design reviews while documenting your

Qualifications

• Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Recently completed coursework in digital design and verification; knowledge of microarchitecture and RTL design.
• Familiarity with processor verification concepts: modern ISA, memory ordering, cache coherency.

Responsibilities

• Develop verification plans for the CPU core and cache hierarchy.
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for the assigned block.
• Build tests, scoreboards, and reference models; close functional and code coverage.
• Triage and root-cause failures with RTL designers under mentorship.
• Participate in design and verification reviews and document the verification environment and results.

Skills

SystemVerilog

UVM

Python

C/C++

Education

BS/MS in Electrical Engineering or related

Tools

Verilog/VHDL simulators

Job description

RosaicLabs Inc. in Santa Clara, CA is seeking an undergraduate or graduate student for an internship/co-op in hardware verification.

You will develop verification plans for CPU cores and cache hierarchies under a mentor, write and debug SystemVerilog/UVM testbenches, and build scoreboards and references to close coverage. You will gain hands-on exposure to chip design and verification, work with RTL designers to triage failures, and participate in design reviews while documenting your