RISC-V CPU IP Intern — Design & Verification

GlobalFoundries; Austin (CA); On-site; USD 28,000 - 55,000; Full time

Job summary

GlobalFoundries is seeking interns for hands-on experience in the design and verification of advanced RISC-V processor IP. You will collaborate with CPU architects, RTL designers, and verification engineers on microarchitecture, RTL implementation, functional verification, performance analysis, automation, and debugging in Austin, Texas or Santa Clara, California.

The role emphasizes hands-on learning, mentorship, and exposure to CPU power, performance, and area optimization while developing

Qualifications

• Education – At least a sophomore at time of application and actively pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field through an accredited degree program during the time of internship.
• Must have at least an overall 3.0 GPA and be in good academic standing.
• Language Fluency - English (Written & Verbal)
• Ability to work at least 40 hours per week during the internship.
• Coursework or project experience in digital logic design and computer architecture.
• Familiarity with Verilog or SystemVerilog.
• Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy.
• Programming or scripting experience with Python, C/C++, or similar languages.
• Strong analytical, problem-solving, and debugging skills.

Responsibilities

• Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development.
• Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts.
• Develop verification tests, assertions, checkers, and functional coverage for CPU features.
• Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms.
• Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases.
• Support CPU power, performance, and area analysis and optimization.
• Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
• Document technical results and communicate findings to the engineering team.

Skills

RISC-V

SystemVerilog

Python

C/C++

Verilog

CPU architecture

Automation

Education

Sophomore status in Bachelor/Master/PhD in Electrical/Computer Engineering

Tools

SystemVerilog/UVM

Git

Linux

Job description

GlobalFoundries is seeking interns for hands-on experience in the design and verification of advanced RISC-V processor IP. You will collaborate with CPU architects, RTL designers, and verification engineers on microarchitecture, RTL implementation, functional verification, performance analysis, automation, and debugging in Austin, Texas or Santa Clara, California.

The role emphasizes hands-on learning, mentorship, and exposure to CPU power, performance, and area optimization while developing