CPU Design Verification Engineer Intern

New Grad; Santa Clara (CA); On-site; USD 28,000 - 41,000; Part time

Job summary

New Grad is offering a hardware verification internship/co-op focused on CPU core and cache hierarchy verification. You will work with a mentor to develop verification plans, write and debug SystemVerilog/UVM testbenches, and build coverage.

This role provides hands-on exposure to chip design and verification and is ideal for EE/CompE students curious about how CPU cores, caches, and memory systems come together.

Qualifications

• Pursuing BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification.
• Familiarity with verifying processor designs, such as: a modern ISA; out-of-order execution and memory ordering; cache coherency and virtual memory.
• Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage.
• Understanding of the end-to-end ASIC design flow and general VLSI concepts.
• Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus

Responsibilities

• Develop verification plans for the CPU core and cache hierarchy
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
• Build tests, scoreboards, and reference models, and close functional and code coverage
• Triage and root-cause failures with RTL designers, with mentorship from senior engineers
• Participate in design and verification reviews and document your verification environment and results

Skills

SystemVerilog

UVM

Testbench development

Regression automation

Python

Perl

Tcl

C/C++

Digital design

Verification

Education

BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

SystemVerilog

UVM

Python

Perl

Tcl

Job description

Join our hardware team as an intern or co-op verifying the CPU core and cache hierarchy, with hands-on ownership of verification environments from test plan through coverage closure and bring-up. Get hands-on exposure to chip design and verification - perfect for EE/CompE students curious about how it all comes together.

What you'll do

• Work with your mentor to develop verification plans for the CPU core and cache hierarchy
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
• Build tests, scoreboards, and reference models, and close functional and code coverage
• Triage and root-cause failures with RTL designers, with mentorship from senior engineers
• Participate in design and verification reviews and document your verification environment and results

Requirements

• Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
• Familiarity with verifying processor designs, such as: a modern ISA; out-of-order execution and memory ordering; cache coherency and virtual memory
• Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
• Understanding of the end-to-end ASIC design flow and general VLSI concepts
• Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus