CPU Design Verification Engineer - Intern

RosaicLabs Inc; Santa Clara (CA); On-site; USD 28,000 - 41,000; Full time

Job summary

RosaicLabs Inc. in Santa Clara, CA is seeking an undergraduate or graduate student for an internship/co-op in hardware verification.

You will develop verification plans for CPU cores and cache hierarchies under a mentor, write and debug SystemVerilog/UVM testbenches, and build scoreboards and references to close coverage. You will gain hands-on exposure to chip design and verification, work with RTL designers to triage failures, and participate in design reviews while documenting your

Qualifications

• Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Recently completed coursework in digital design and verification; knowledge of microarchitecture and RTL design.
• Familiarity with processor verification concepts: modern ISA, memory ordering, cache coherency.

Responsibilities

• Develop verification plans for the CPU core and cache hierarchy.
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for the assigned block.
• Build tests, scoreboards, and reference models; close functional and code coverage.
• Triage and root-cause failures with RTL designers under mentorship.
• Participate in design and verification reviews and document the verification environment and results.

Skills

SystemVerilog

UVM

Python

C/C++

Education

BS/MS in Electrical Engineering or related

Tools

Verilog/VHDL simulators

Job description

Join our hardware team as an intern or co-op verifying the CPU core and cache hierarchy, with hands-on ownership of verification environments from test plan through coverage closure and bring-up.

Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together.

What you'll do

• Work with your mentor to develop verification plans for the CPU core and cache hierarchy
• Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
• Build tests, scoreboards, and reference models, and close functional and code coverage
• Triage and root-cause failures with RTL designers, with mentorship from senior engineers
• Participate in design and verification reviews and document your verification environment and results

Requirements

• Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
• Familiarity with verifying processor designs, such as: a modern ISA; out-of-order execution and memory ordering; cache coherency and virtual memory
• Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
• Understanding of the end-to-end ASIC design flow and general VLSI concepts
• Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.