CPU Core Physical Design Intern – Hybrid, Folsom

Intel Corporation; Folsom, Northern (CA, KY); Hybrid; USD 106,000 - 107,000; Full time

Job summary

Intel Corporation in Folsom, CA is seeking a 2027 Physical Design Engineering Graduate Intern to contribute to silicon implementation, including synthesis, place & route, timing, and clocking. You will help verification and signoff, ensuring manufacturability while collaborating with cross-functional teams on scalable design automation.

The role targets a Master's student in EE/CE with experience in digital IC design, VLSI flows, and scripting in Python/Perl/Tcl, with relocation possible and a

Qualifications

• Pursuing a Master's degree in EE, CE, or related field.
• Coursework or projects in digital IC design and VLSI physical design.
• Fundamental knowledge of logic synthesis, place & route, and STA.
• Experience with Perl, Tcl, or Python.
• Understanding of ASIC/SoC design flows.

Responsibilities

• Support physical design implementation including synthesis, place & route, and integration.
• Conduct timing analysis and clocking to optimize performance.
• Assist in verification and signoff activities for manufacturability.
• Collaborate with cross-functional teams to improve design automation.
• Apply knowledge through hands-on tasks aligned with Intel goals.

Skills

Digital IC design

VLSI physical design

Scripting: Python/Perl/Tcl

Synthesis/Place & Route

Timing analysis (STA)

ASIC/SoC flows

Academic project experience

Education

Master's degree in Electrical Engineering / Computer Engineering

Tools

EDA tools

Python

Perl

Tcl

Job description

Intel Corporation in Folsom, CA is seeking a 2027 Physical Design Engineering Graduate Intern to contribute to silicon implementation, including synthesis, place & route, timing, and clocking. You will help verification and signoff, ensuring manufacturability while collaborating with cross-functional teams on scalable design automation.

The role targets a Master's student in EE/CE with experience in digital IC design, VLSI flows, and scripting in Python/Perl/Tcl, with relocation possible and a