CPU Core Physical Design Technical Graduate Intern, Spring

Intel; Folsom (CA); Hybrid; USD 106,000 - 107,000; Part time

Job summary

Intel in US California is seeking a 2027 Physical Design Engineering Graduate Intern to contribute to the physical implementation of silicon designs, including synthesis, place and route, timing, clocking, and integration. You will assist in verification and signoff to ensure manufacturability and performance compliance, aligning with Intel's innovation goals.

Ideal candidates are local to Folsom or willing to relocate for a semester away, with a strong foundation in digital IC design, VLSI, and

Qualifications

• Master's degree pursuit in EE/CE or related field.
• Coursework or projects in digital IC design and VLSI physical design.
• Fundamental knowledge of logic synthesis, P&R, and STA.
• Experience with Perl, Tcl, or Python scripting.
• Understanding of ASIC/SoC design flows and EDA tools.

Responsibilities

• Support physical design implementation including synthesis, place and route, and integration.
• Conduct timing analysis and clocking to optimize performance.
• Assist in verification and signoff to ensure manufacturability.
• Collaborate with cross functional teams to improve design scalability and automation.
• Learn through hands-on tasks aligned with Intel's goals.

Skills

Digital IC design

VLSI design

Scripting languages

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

Perl

Tcl

Python

Job description

Job Description

The Role and Impact

As a 2027 Physical Design Engineering Graduate Intern, you will contribute to the physical implementation of silicon designs to create manufacturing-ready solutions. Your day-to-day work will involve tasks such as synthesis, place and route, timing analysis, clocking, and/or integration. By assisting in verification and signoff activities, you will ensure manufacturability and performance compliance, directly supporting Intel's broader innovation goals.

Business Group

The Data Center Group (DCG) is at the forefront of transforming data-centric technologies by delivering solutions that power Intel's silicon and platform advancements. Focused on high-performance computing, storage, and connectivity, DCG plays a vital role in shaping Intel's impact across industries, enabling scalable, automated, and impactful designs for modern infrastructure challenges.

Duration

January 2027 - August 2027

Ideal candidate is local to Folsom area or will arrange for a semester away.

Relocation is available.

Key Responsibilities

• Support physical design implementation, including synthesis, place and route, and integration.
• Conduct timing analysis and clocking to optimize design performance.
• Assist in verification and signoff activities to ensure manufacturability and compliance.
• Collaborate with cross-functional teams to enhance design scalability and automation.
• Learn and apply knowledge through hands‑on tasks and projects aligned with Intel's goals.

Qualifications

Minimum Qualifications

• Pursuing a Master's degree in Electrical Engineering (EE), Computer Engineering (CE), or a related field.
• Coursework, academic projects, or research experience in digital integrated circuit design and VLSI physical design.
• Fundamental knowledge of logic synthesis, place and route, and static timing analysis (STA).
• Experience with one or more scripting/programming languages such as Perl, Tcl, or Python.
• Understanding of semiconductor design flows and ASIC/SoC implementation concepts.

Preferred Qualifications

• Experience with synthesis, place and route, and timing analysis.
• Knowledge of low‑power design techniques and PPA optimization.
• Programming experience with Perl, Tcl, and/or Python.
• Familiarity with ASIC/SoC physical design flows and EDA tools.
• Experience from coursework, research, or projects in VLSI or semiconductor design.

Job Type

Student / Intern

Shift

Shift 1 (United States of America)

Primary Location

US, California, Folsom

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range

Annual Salary Range for jobs which could be performed in the US: $105,698.00-105,702.00 USD

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.

* Job posting details (such as work model, location or time type) are subject to change.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.