Mid-Level Physical Design Engineer - CPU Cores

Intel Corporation; Hillsboro, Northern (OR, KY); Hybrid; USD 122,000 - 232,000; Full time

Job summary

Intel Corporation in Hillsboro, Oregon seeks a Mid-level Physical Design Engineer for CPU cores, contributing to RTL-to-GDS flow with responsibilities across synthesis, floorplanning, PnR, STA, and design closure. You will work with RTL, verification, clocking, and full-chip teams to meet PPA targets.

The role emphasizes scripting (TCL, Python) for automation, design flow improvements, and continuous learning in a fast-paced semiconductor environment.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field with 5+ years of relevant work experience.
• Or a Master's in the same field with 3+ years of relevant work experience.
• Experience with integrated circuit design tools (e.g., Synopsys/Cadence) including logic synthesis, place and route, STA and design closure.
• PV convergence including static timing and power analysis.
• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electromigration checks.
• Scripting in TCL and at least one other language (e.g., Python).
• Experience with Synthesis of a digital block integrated into a large SoC or IP.

Responsibilities

• Execute physical design implementation for CPU core blocks or subsystems.
• Perform synthesis, floor planning, place and route, and design closure activities.
• Conduct STA, power analysis, and physical verification.
• Identify and debug timing, power, and design rule violations.
• Contribute to achieving timing, power, and area targets.
• Develop and maintain scripts for design automation (TCL, Python).
• Collaborate with RTL, verification, clocking, and full-chip teams.
• Support improvements to design flows, methodologies, and best practices.
• Document technical work and share knowledge within the team.

Skills

TCL scripting

Python scripting

Static timing analysis

Power analysis

Place & Route

DRC/LVS

Synthesis

Clock distribution

Education

Bachelor's in Electrical/Computer Engineering

Master's in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler

ICC2

PrimeTime

Cadence Genus

Cadence Innovus

Job description

Intel Corporation in Hillsboro, Oregon seeks a Mid-level Physical Design Engineer for CPU cores, contributing to RTL-to-GDS flow with responsibilities across synthesis, floorplanning, PnR, STA, and design closure. You will work with RTL, verification, clocking, and full-chip teams to meet PPA targets.

The role emphasizes scripting (TCL, Python) for automation, design flow improvements, and continuous learning in a fast-paced semiconductor environment.