Engineer, Staff|6314 Engineer, Staff|6314

ALTEN; San Diego (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

ALTEN is looking for a Physical Design Engineer in San Diego. You will develop, implement, and verify high-speed processor cores, requiring expertise in STA closure and Place and Route. Candidates should have 8-12 years of experience in Physical Design and a Bachelor's degree in a relevant field. The role demands deep knowledge of tools like Cadence Innovus and Synopsys ICC2. This position is on-site once the staff returns to campus, offering an opportunity to work on cutting-edge FinFet technologies.

Qualifications

• Candidates must have 8-12 years of direct relevant experience in Physical Design.
• This position requires 2-5 years of experience with STA closure and Place and Route.
• Hands on experience with the latest FinFet technologies (20nm and below) is needed.

Responsibilities

• Develop, implement, and verify high-speed processor cores using state-of-the-art tools.
• Responsible for the complete Physical Design Flow for high-speed processor cores.
• Debugging timing violations for multi-mode and multi-corner designs.

Skills

STA closure

Place and Route

Functional verification

Scripting (PERL/TCL)

Linux/Unix shell

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Electrical Engineering

Tools

Cadence Innovus

Synopsys ICC2

Synopsys PTSI

Job description

Job Description:

This position requires 2-5 years of experience with STA closure and Place and Route. Exposure to ICC, Innovus, and/or Prime Time is needed. Hands on experience with the latest FinFet technologies (20nm and below) is needed.

Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our CPU core design team. As a high‑speed physical design engineer you will develop, implement, and verify high‑speed processor cores using state‑of‑the‑art tools and technologies.

You will be part of a team responsible for the complete Physical Design Flow for high‑speed processor cores. Tasks involve the development and enablement of low‑power implementation methods, customized P&R to achieve area reduction and performance goals, and the development of high‑speed customized logic cells.

Additional responsibilities in this role involve a good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi‑mode & multi‑corner (MMMC) clock tree synthesis, routing, timing optimization, 2.5D RC extraction, signal integrity, cross‑talk noise and delay analysis, debugging timing violations for multi‑mode and multi‑corner designs, implementing timing fixes, rolling in functional ECOs, physical verification (drc, lvs, antenna), debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and deliver complex modem CPU Physical Design solutions from netlist and timing constraints to the final product.

Minimum Qualifications:

• Candidates must have 8-12 years of direct relevant experience in Physical Design, floorplanning, P&R, formal verification, and/or physical verification.
• This position requires 2-5 years of experience with STA closure and Place and Route. Exposure to ICC, Innovus, and/or Prime Time is needed. Hands on experience with the latest FinFet technologies (20nm and below) is needed.

Education:

• Required - Bachelor's degree in Science, Engineering, or related field.

Preferred Qualifications:

• 8+ years of direct industry experience in Physical Design.
• Place & Route tool experience on Cadence Innovus and/or Synopsys ICC2.
• Timing closure experience in Synopsys PTSI.
• Formal verification experience.
• Physical verification experience.
• Master's degree in Electrical Engineering.

Location Requirements:

Must be local to San Diego, Bay Area or Austin, TX. Will be required to come on‑site once staff returns to campus.