CPU Core Physical Design Intern: Synthesis to Signoff

Intel Corporation; Folsom (CA); Hybrid; USD 106,000 - 107,000; Full time

Job summary

Intel Corporation in the United States seeks a 2027 Physical Design Engineering Graduate Intern to contribute to the physical implementation of silicon designs, including synthesis, place and route, timing analysis, clocking, and integration.

You will support verification and signoff activities to ensure manufacturability and performance, collaborate with cross-functional teams, and apply hands-on tasks aligned with Intel's goals in a hybrid work model.

Qualifications

• Pursuing a Master’s degree in Electrical or Computer Engineering with a focus on VLSI.
• Coursework or research in digital IC design and physical design flows.
• Fundamental knowledge of logic synthesis, place&route, and STA.
• Experience with Perl, Tcl, or Python scripting.

Responsibilities

• Support physical design implementation including synthesis, place & route, and integration.
• Conduct timing analysis and clocking to optimize design performance.
• Assist in verification and signoff activities to ensure manufacturability.
• Collaborate with cross-functional teams to enhance design scalability and automation.
• Learn through hands-on tasks aligned with Intel's goals.

Skills

Digital IC design

Python

Perl

Tcl

STA (Static Timing Analysis)

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

Synthesis tools

Place & Route tools

Timing analysis tools

Job description

Intel Corporation in the United States seeks a 2027 Physical Design Engineering Graduate Intern to contribute to the physical implementation of silicon designs, including synthesis, place and route, timing analysis, clocking, and integration.

You will support verification and signoff activities to ensure manufacturability and performance, collaborate with cross-functional teams, and apply hands-on tasks aligned with Intel's goals in a hybrid work model.