Physical Design Intern: Floorplanning & Timing for 7nm Chips

Ampere Computing; Santa Clara (CA); On-site; USD 76,000 - 83,000; Full time

Benefits offered by this job

Mentorship

Healthy snacks

Ergo desk

Game rooms

On-the-job training

Job summary

Ampere Computing invites applications for a full-time fall 2026 internship focused on physical design of high-performance processor blocks. You will join a growing team and contribute to timing closure, CAD flows, and design verification, gaining hands-on experience across ASIC methodologies.

Ideal candidates are pursuing a Master’s in Electrical Engineering with VLSI focus, have strong scripting skills, and are eager to advance in a cutting-edge AI compute environment.

Qualifications

• Pursuing a master's in Electrical Engineering with VLSI focus.
• Experience in floor planning, place & route, and timing constraints.
• Familiarity with high-speed design and CMOS 7nm rules.
• Knowledge of STA, EM/IR and sign-off flow.
• Proficiency in Tcl and Python scripting.

Responsibilities

• Design and implement large partitions of processor blocks.
• Run synthesis, placement, CTS, routing for block prep.
• Automate workflows with EDA scripting.
• Develop lower-geometry designs using 7nm CMOS rules.
• Work with design libraries and macro-compilers.

Skills

Floor planning

Place & route

Power distribution

Timing constraints

STA/EM/IR

Tcl/Python scripting

Education

Master's in Electrical Engineering

Tools

EDA tools

Job description

Ampere Computing invites applications for a full-time fall 2026 internship focused on physical design of high-performance processor blocks. You will join a growing team and contribute to timing closure, CAD flows, and design verification, gaining hands-on experience across ASIC methodologies.

Ideal candidates are pursuing a Master’s in Electrical Engineering with VLSI focus, have strong scripting skills, and are eager to advance in a cutting-edge AI compute environment.