Physical Design Intern: Silicon Timing & Synthesis

Intel; Folsom (CA); Hybrid; USD 106,000 - 107,000; Part time

Job summary

Intel in US California is seeking a 2027 Physical Design Engineering Graduate Intern to contribute to the physical implementation of silicon designs, including synthesis, place and route, timing, clocking, and integration. You will assist in verification and signoff to ensure manufacturability and performance compliance, aligning with Intel's innovation goals.

Ideal candidates are local to Folsom or willing to relocate for a semester away, with a strong foundation in digital IC design, VLSI, and

Qualifications

• Master's degree pursuit in EE/CE or related field.
• Coursework or projects in digital IC design and VLSI physical design.
• Fundamental knowledge of logic synthesis, P&R, and STA.
• Experience with Perl, Tcl, or Python scripting.
• Understanding of ASIC/SoC design flows and EDA tools.

Responsibilities

• Support physical design implementation including synthesis, place and route, and integration.
• Conduct timing analysis and clocking to optimize performance.
• Assist in verification and signoff to ensure manufacturability.
• Collaborate with cross functional teams to improve design scalability and automation.
• Learn through hands-on tasks aligned with Intel's goals.

Skills

Digital IC design

VLSI design

Scripting languages

Education

Master's degree in Electrical Engineering or Computer Engineering

Tools

Perl

Tcl

Python

Job description

Intel in US California is seeking a 2027 Physical Design Engineering Graduate Intern to contribute to the physical implementation of silicon designs, including synthesis, place and route, timing, clocking, and integration. You will assist in verification and signoff to ensure manufacturability and performance compliance, aligning with Intel's innovation goals.

Ideal candidates are local to Folsom or willing to relocate for a semester away, with a strong foundation in digital IC design, VLSI, and