Chiplet Packaging Engineer: 2.5D/3D Integration Leader

Rapidus Corporation US; Santa Clara (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Global collaboration

Next-gen nodes exposure

Comprehensive health coverage

Competitive compensation

Job summary

Rapidus Corporation US in Santa Clara, CA, Albany, NY, Tokyo and Chitose, Japan, seeks a Chiplet Package Design Engineer to drive 2.5D/3D heterogeneous integration for next‑generation semiconductor products.

You will lead design, synthesis, and P&R, collaborate with silicon, packaging, and OSAT partners, and push AI/ML-driven design space exploration across global teams. The role offers exposure to 2nm technology and a competitive, full‑time package.

Qualifications

• 5+ years of semiconductor package design experience.
• Hands-on with 2.5D/3D packaging technologies.
• Strong knowledge of high-speed interfaces and SI/PI.
• Experience with OSAT ecosystem and packaging processes.
• Cross-functional collaboration across global teams.

Responsibilities

• Lead the design and development of 2.5D/3D package architectures (interposer-based, fan-out, 3D stacking).
• Define and optimize chiplet integration strategies (die partitioning, interface definition, interconnect topologies).
• Develop package layout and routing for high-speed interconnects (HBM, UCIe, PCIe, SerDes).
• Perform and guide signal integrity, power integrity, and thermal analysis.
• Collaborate with silicon teams on bump/pad design, floorplanning, and co-design methodologies.
• Drive package-substrate co-design including material selection and stack-up definition.
• Interface with OSATs and foundries for manufacturability, yield improvement, cost optimization.
• Support DFx (DFM, DFT, DFA) and reliability validation (warpage, stress, electromigration).
• Contribute to package technology roadmap for advanced nodes (2nm and beyond).
• Participate in bring-up, validation, and failure analysis of packaged devices.

Skills

Semiconductor package design

2.5D/3D packaging

Cross-functional collaboration

High-speed interfaces

OSAT ecosystem knowledge

Education

Bachelor's or Master's in Electrical/Mechanical/Materials or related field

Tools

Cadence Allegro Package Designer

Sigrity

Ansys HFSS

RedHawk-SC Electrothermal

Job description

Rapidus Corporation US in Santa Clara, CA, Albany, NY, Tokyo and Chitose, Japan, seeks a Chiplet Package Design Engineer to drive 2.5D/3D heterogeneous integration for next‑generation semiconductor products.

You will lead design, synthesis, and P&R, collaborate with silicon, packaging, and OSAT partners, and push AI/ML-driven design space exploration across global teams. The role offers exposure to 2nm technology and a competitive, full‑time package.