Optical Chip Packaging Architect – 2.5D/3D Lead R&D

Asteralabs; San Jose (CA); On-site; USD 205,000 - 260,000; Full time

Job summary

Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips in San Jose. This senior individual contributor role focuses on setting technical direction and driving packaging technology development for NPO and CPO products.

You will define and optimize wafer-, panel-, or die-level packaging flows, drive EIC-to-PIC integration, select materials, and collaborate with OSATs and suppliers to advance equipment and processes.

Qualifications

• 8+ years of experience in semiconductor or advanced packaging engineering with leadership.
• Deep expertise in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold across wafer-, panel-, and die-level flows.
• Experience with silicon photonics chip packaging and EIC/PIC integration.
• Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.
• Proven track record of equipment and process qualification with OSAT or tool suppliers.
• Experience with PDK development and packaging design rule authoring.
• Strong foundation in yield analysis, reliability characterization, and process capability methodologies such as Cpk and SPC.

Responsibilities

• Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
• Define and optimize wafer-level, panel-level, or die-level packaging process flows.
• Drive EIC-to-PIC integration and broader optical device integration efforts.
• Select and qualify packaging materials for advanced packaging.
• Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.
• Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.
• Develop and maintain packaging PDKs and design rules for NPO and CPO products.

Skills

Advanced packaging engineering

Technical leadership

2.5D/3D packaging

Flip-chip & hybrid bonding

OSAT collaboration

Packaging design rules (PDK)

Yield analysis & reliability

Education

B.S./M.S./Ph.D. in Electrical/Materials/Mechanical Engineering or related

Tools

PDK development tools

Packaging design tools

Job description

Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips in San Jose. This senior individual contributor role focuses on setting technical direction and driving packaging technology development for NPO and CPO products.

You will define and optimize wafer-, panel-, or die-level packaging flows, drive EIC-to-PIC integration, select materials, and collaborate with OSATs and suppliers to advance equipment and processes.