Lead 2.5D/3D Chiplet Package Architect

Rapidus Corporation US

Santa Clara (CA)

Vor Ort

USD 150.000 - 230.000

Vollzeit

vor 43 Stunden
Sei unter den ersten Bewerbenden

Eine vollständige Bewerbung in einer Minute

Maßgeschneiderter Lebenslauf und Anschreiben – versandbereit.

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Benefits dieser Stelle

Health, dental and vision coverage
Career growth opportunities
Global collaboration

Zusammenfassung

Rapidus Corporation US is seeking a Chiplet Package Design Engineer to drive 2.5D/3D heterogeneous integration across multiple locations, including Santa Clara, Albany, and beyond. You will collaborate with silicon design, OSAT partners, and manufacturing to deliver cutting-edge chiplet-based packaging solutions.

The role emphasizes synthesis and PnR in the digital reference flow, with adoption of AI-driven design space exploration and next‑gen automation tools.

Qualifikationen

  • Bachelor's or Master's in EE, ME, Materials Science or related field.
  • 5+ years in semiconductor package design, advanced packaging experience.
  • Hands-on with 2.5D/3D packaging technologies (silicon interposer, TSV, hybrid bonding).
  • Strong knowledge of high-speed interfaces and package-level SI/PI considerations.
  • Experience with industry-standard tools like Cadence Allegro, Sigrity, Ansys HFSS.

Aufgaben

  • Lead design and development of 2.5D/3D package architectures (interposer-based, fan-out, 3D stacking).
  • Define and optimize chiplet integration strategies including die partitioning and interconnect topologies.
  • Develop package layout and routing for high-density interconnects (HBM, UCIe, PCIe, SerDes).
  • Perform SI, PI, and thermal analyses; guide reliability validation.

Kenntnisse

Chiplet packaging
2.5D/3D packaging
High-speed interfaces
SI/PI analysis
Cross-functional collaboration

Ausbildung

B.S./M.S. in Electrical/Mechanical Materials

Tools

Cadence Allegro Package Designer
Sigrity
Ansys HFSS
RedHawk-SC Electrothermal

Jobbeschreibung

Rapidus Corporation US is seeking a Chiplet Package Design Engineer to drive 2.5D/3D heterogeneous integration across multiple locations, including Santa Clara, Albany, and beyond. You will collaborate with silicon design, OSAT partners, and manufacturing to deliver cutting-edge chiplet-based packaging solutions.

The role emphasizes synthesis and PnR in the digital reference flow, with adoption of AI-driven design space exploration and next‑gen automation tools.

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