Remote Package Design Engineer – 2.5D/3.5D HPC

SPD Technology

United States

A distancia

USD 140.000 - 210.000

Jornada completa

Hace 8 días

Una candidatura completa en un minuto

Currículum y carta de presentación personalizados, listos para enviar.

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Descripción de la vacante

SPD Technology is seeking a Package Design Engineer to join our Silicon Integration team. You will develop package substrate designs for 2.5D/3.5D packaging technologies used in high‑performance ML and AI chips, collaborating with SI/PI, thermal, mechanical, and PCB teams to optimize electrical performance and manufacturability.

The role covers routing feasibility, test vehicles, product-level designs, design reviews, and manufacturing documentation, with global, fully remote work and a focus on

Formación

  • Bachelor's degree in Mechanical Engineering, Materials Engineering, Electrical Engineering, Technology, Science, or related field.
  • 8 years of experience in chip package substrate design using Cadence APD or Mentor Expedition.
  • Experience in chip package substrate layout, design verification, DFM and taping out for production.
  • Experience in design automation and scripting.
  • English — Upper Intermediate or higher.

Responsabilidades

  • Develop package substrate designs for large form-factor packages for ML HPCs.
  • Define and implement CAD flow for efficient substrate design and productivity.
  • Lead co-design initiatives across chip, package, and system levels with production sign-off.
  • Collaborate with SI/PI, thermal, and mechanical teams to refine product designs.
  • Define requirements for package substrate design and BOM.

Conocimientos

Chip package design
Cadence APD
Mentor Expedition
Design verification
Scripting
English proficiency

Educación

Bachelor's degree in Mechanical or Electrical Engineering or related

Herramientas

Cadence APD
Mentor Expedition

Descripción del empleo

SPD Technology is seeking a Package Design Engineer to join our Silicon Integration team. You will develop package substrate designs for 2.5D/3.5D packaging technologies used in high‑performance ML and AI chips, collaborating with SI/PI, thermal, mechanical, and PCB teams to optimize electrical performance and manufacturability.

The role covers routing feasibility, test vehicles, product-level designs, design reviews, and manufacturing documentation, with global, fully remote work and a focus on

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