Senior Package Designer for 2.5D/3.5D HPC Substrates Remote

Spd-Technology; United States; Remote; USD 120,000 - 180,000; Full time

Benefits offered by this job

Fully remote

Flexible schedule

Job summary

Spd-Technology is seeking a Package Design Engineer to join our Silicon Integration team, focusing on developing package substrate designs for advanced 2.5D/3.5D packaging used in high-performance ML and AI chips. You will collaborate with SI/PI, Thermal/Mechanical, and PCB teams to optimize electrical performance, reliability, and manufacturability.

The role covers all phases from routing feasibility and test vehicles to manufacturing documentation and BOM definitions.

Qualifications

• Bachelor's degree in engineering or related field.
• 8 years of chip package substrate design experience.
• Experience with Cadence APD or Mentor Expedition and DFM.
• Experience in design automation and scripting.

Responsibilities

• Develop package substrate designs for 2.5D/3.5D packaging.
• Collaborate with SI/PI, Thermal/Mechanical, Assembly, and PCB teams.
• Manage routing feasibility studies and manufacturing documentation.
• Drive design reviews and BOM documentation.
• Evaluate and adopt advanced chip packaging technologies.

Skills

Chip package substrate design

Design automation

Scripting

Education

Bachelor's degree in engineering or related field

Tools

Cadence APD

Mentor Expedition

Job description

Spd-Technology is seeking a Package Design Engineer to join our Silicon Integration team, focusing on developing package substrate designs for advanced 2.5D/3.5D packaging used in high-performance ML and AI chips. You will collaborate with SI/PI, Thermal/Mechanical, and PCB teams to optimize electrical performance, reliability, and manufacturability.

The role covers all phases from routing feasibility and test vehicles to manufacturing documentation and BOM definitions.