Chip-Design FE Engineer: RTL, Synthesis & Timing

Apple Inc.; Austin (TX); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Apple Inc. in Austin, Texas, is seeking an experienced hardware engineer to optimize and implement chip designs for cutting-edge devices. The role focuses on synthesis, timing constraints, power integrity, and signoff, ensuring robust physical design across FPGA/ASIC-like workflows.

You will collaborate with CAD teams to resolve issues, apply ECOs, and push for low power, small area, and high-performance results while maintaining RTL validity and verification using industry-standard tools.

Qualifications

• Master’s degree in Electrical & Computer Engineering or related field with 2 years of experience.
• Experience using VLSI design and timing to evaluate engineering tradeoffs.
• Proficiency with HDL to understand and improve designs.
• Scripting in Perl and Python to automate tasks.
• Apply physical design concepts to improve timing and reduce congestion.
• Experience with synthesis techniques and Boolean optimization to recover area and power, and fix setup/hold timing violations.
• RTL and Netlist validation using simulation and debugging tools.
• Understanding GPU architectures to guide dataflow and optimization.

Responsibilities

• Optimize and implement chip designs for hardware devices.
• Design synthesis to convert RTL to digital logic gates.
• Perform static timing analysis and constraint development.
• Work on power integrity checks and signoff flows for chip designs.
• Collaborate with CAD team and tool vendors to resolve flow or integration issues.
• Create innovative flows to support new chip designs.
• Optimize logic for low power, low area, high performance, and timing goals.

Skills

VLSI design

HDL

Perl scripting

Python scripting

Synthesis techniques

Boolean optimization

RTL/Netlist validation

GPU architectures

Timing optimization

Physical design concepts

Education

Master's in Electrical & Computer Engineering

Job description

Apple Inc. in Austin, Texas, is seeking an experienced hardware engineer to optimize and implement chip designs for cutting-edge devices. The role focuses on synthesis, timing constraints, power integrity, and signoff, ensuring robust physical design across FPGA/ASIC-like workflows.

You will collaborate with CAD teams to resolve issues, apply ECOs, and push for low power, small area, and high-performance results while maintaining RTL validity and verification using industry-standard tools.