SOC Physical Design Engineer: From Netlist to Tape-out

Apple; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple in Austin, Texas is seeking a Senior Physical Design Engineer to drive SOC blocks from netlist to tape-out, optimizing power, performance and area.

You will collaborate with RTL and FE teams, implement clock and power distribution, run STA/DRC/LVS checks, and develop scripts to streamline design workflows.

The role demands a Master’s in EE and 5+ years in EDA flows, with hands-on experience in Innovus, IC Compiler, PrimeTime or Calibre.

Qualifications

• Master's degree in Electrical Engineering or related field with 5 years of related experience.
• Experience with EDA tools like Innovus or IC Compiler.
• Experience in synthesis, place-and-route, or verification flows.
• Ability to interpret timing constraints for convergence and low power verification.
• Proficiency in HDL and scripting to automate tasks.

Responsibilities

• Perform physical design of SOC blocks from netlist to tape-out in advanced nodes.
• Collaborate with RTL and FE teams to optimize power, area, and timing.
• Develop scripts to automate design data extraction and analysis.
• Analyze STA, IR drop, LVS/DRC violations and fix issues.

Skills

Synthesis

Automated place & route

Verification flows

Timing convergence

Low power verification

Hardware description languages

Scripting (Perl)

Shell scripting

Makefiles

TCL

Education

Master's degree in Electrical Engineering or related field

Tools

Innovus

IC Compiler

Primetime

Calibre

Job description

Apple in Austin, Texas is seeking a Senior Physical Design Engineer to drive SOC blocks from netlist to tape-out, optimizing power, performance and area.

You will collaborate with RTL and FE teams, implement clock and power distribution, run STA/DRC/LVS checks, and develop scripts to streamline design workflows.

The role demands a Master’s in EE and 5+ years in EDA flows, with hands-on experience in Innovus, IC Compiler, PrimeTime or Calibre.