SoC Front-End Implementation Engineer: Synthesis, Power, RTL

Apple Inc.; Cupertino (CA); On-site; USD 150,000 - 278,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock programs

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. in Cupertino, CA, is hiring an SOC/ASIC Front-End Implementation Engineer to drive front-end integration, synthesis, UPF details, and timing closure for multi-million gate ASICs.

The role emphasizes low-power design, power intent verification at chip level, and close collaboration with SOC teams. Strong scripting skills (Perl/Tcl/Python) and excellent communication are preferred.

Qualifications

• BS degree + 3 years of industry experience required.
• Expertise in digital design integration, synthesis, UPF, timing analysis, and closure.
• Hands-on experience across chip development with frontend tools and methodologies.
• Scripting experience in Perl, Tcl, or Python is a plus.
• RTL design or implementation on multi-million gate ASICs is a plus.

Responsibilities

• Drive all front-end integration activities: integration, synthesis, UPF, logical equivalence, ECO, etc.
• Improve synthesis QOR through methodology improvements and low-power design
• Work on RTL integration, timing constraints, and synthesis of designs
• Collaborate with SOC Design, Verification, Emulation, STA, Power, and Physical Design teams

Skills

Digital design integration

Synthesis

UPF

Timing analysis

Closure

Front-end tools

Scripting (Perl/Tcl/Python)

RTL logic design

Communication

AI tools awareness

Education

BS degree

Tools

LEQ

Lint

Job description

Apple Inc. in Cupertino, CA, is hiring an SOC/ASIC Front-End Implementation Engineer to drive front-end integration, synthesis, UPF details, and timing closure for multi-million gate ASICs.

The role emphasizes low-power design, power intent verification at chip level, and close collaboration with SOC teams. Strong scripting skills (Perl/Tcl/Python) and excellent communication are preferred.