RTL Design Engineer — ASIC & PMIC Power

Apple Inc.; Cupertino (CA); Híbrido; USD 150.000 - 225.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Stock programs

Medical & dental

Relocation assistance

Educational reimbursement

Descripción de la vacante

Apple Inc. in Cupertino, California, seeks a senior RTL/ASIC designer to deliver complex digital IPs for PMICs. You will design digital logic in SystemVerilog, collaborate with cross-functional teams, and drive PPA-aware implementation from RTL to gate-level.

The role involves clock domain crossing and reset domain checks, signoff duties, and scripting in Perl/Python, with opportunities for relocation and growth in a leading hardware team.

Formación

• Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
• Experience designing digital logic in ASIC using SystemVerilog.
• Experience simulating ASIC designs with Cadence or Synopsys SystemVerilog simulators.
• Experience debugging waveform viewers like SimVision or Indago to root out hardware issues.
• Experience synthesizing designs into ASIC library gates using Synopsys Design Compiler or Cadence Genus.

Responsabilidades

• Design digital logic in ASIC using SystemVerilog to meet required behavior.
• Synthesize RTL designs into ASIC gates and optimize for area, power, timing.
• Perform CDC and RDC analysis to ensure reliable data transfer and robust resets.
• Collaborate with cross-functional teams (Analog, Architecture, DFT, ATE) to finalize specs.
• Support tapeout signoff with constraint files and STA reports.
• Provide debugging support to Silicon Validation and explain design functionality.

Conocimientos

SystemVerilog

ASIC design

RTL design

CDC

RDC

Educación

Master’s degree in Electrical and Computer Engineering or related field

Herramientas

Cadence Design Compiler

Cadence Genus

Cadence Xcelium

Synopsys Design Compiler

PrimeTime PX

SimVision

Python

Perl

Descripción del empleo

Apple Inc. in Cupertino, California, seeks a senior RTL/ASIC designer to deliver complex digital IPs for PMICs. You will design digital logic in SystemVerilog, collaborate with cross-functional teams, and drive PPA-aware implementation from RTL to gate-level.

The role involves clock domain crossing and reset domain checks, signoff duties, and scripting in Perl/Python, with opportunities for relocation and growth in a leading hardware team.